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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 95/180頁(yè) |
| 文件大小： | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
95
Zarlink Semiconductor Inc.
4.7.2.2 Synchronous Clocking Circuit
There are two possible options for generating a synchronous clock which is traceable to a Primary Reference
Source (PRS). The first option, referred to as Synchronous Clock #1, is generated via an internal digital PLL. The
second, Synchronous Clock #2, is provided via an external PLL. These options are available for UDT, SDT, and
TDM Backplane modes of operation.
Synchronous Clock #1 (Internal Digital PLL)
Each port within the MT90520 device has its own internal digital PLL. Refer to Section 4.7.2.7, “Internal Digital PLL
Sub-Module,” on page 103 for information regarding the specifics of the design and its operation. This PLL
performs various functions within the MT90520, including SRTS clock recovery (outlined in Section 4.7.2.5),
adaptive clock recovery (described in Section 4.7.2.6), and PRS-traceable clock generation, which is explained
here. Each PLL continuously generates a clock which runs at the TDM line rate.
In this mode, the reference clock for all of the PLLs is provided by an 8 kHz clock, derived as a divided-down
version of the network clock. The generation of this reference clock is explained in Section 4.7.2.3 on page 97. The
implementation of the synchronous clock generation is shown in Figure 35.
Figure 35 - Synchronous Source Multiplied to TDM Bus Rate by Internal PLL
The clock output from the PLL (PLLCLK for each of the DS1/E1 ports) is transmitted to the port’s corresponding
SToCLK multiplexer.
Synchronous Clock #2 (External PLL)
As an alternative to the internal PLL, an external PLL may be used to provide a synchronous clock for transmission
onto the TDM output bus. Using this method, a PRS-traceable signal from an external PLL is input to the MT90520
via the TDM_CLK pin. Since this is a “common” clock signal (i.e., one per device), TDM_CLK is routed to a
multiplexer, as shown previously in Figure 34. The output of this multiplexer is a common clock which is routed to
the clock selection multiplexers (one per port) in the “Interface to TDM sub-module”, detailed previously in
Section 4.7.2.1. The implementation of the synchronous clock generation is shown in Figure 36.
Clock Management Module
Digital
PLL
PLLCLK
8_kHz
MT90520
(generated by Network
Clock Divider Circuit
)
(Synchronous Clock #1)
To “Interface to
TDM Sub-Module”
Multiplexers &
“Synchronous
Clocking Circuit”
Multiplexers
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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