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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 90/180頁(yè) |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
90
Zarlink Semiconductor Inc.
4.7 Clock Management Module
The Clock Management module of the MT90520 is designed to provide both clock control and clock recovery
functions. The primary control function of the module is to generate clock signals and frame pulses to be output via
the MT90520’s TDM interface. With regard to clock recovery, the Clock Management module is responsible for
performing synchronous clock recovery, Synchronous Residual Time Stamp (SRTS) clock recovery, and Adaptive
(ACM) clock recovery, as required to meet the CES specification, af-vtoa-0078.000.
4.7.1 Overview
4.7.1.1 Clock Control
When the DS1/E1 ports of the device are operating in UDT mode, the Clock Management module generates the
per-port PCM output clocks required to interface with LIUs or framer/LIUs, based on a user-selectable clock source.
When operating in SDT mode, the Clock Management module generates the output clock signals as in UDT mode.
However, rather than interfacing with LIUs or framer/LIUs, these signals are output to framer devices.
TDM backplane mode is a sub-set of SDT operation in which the MT90520 device interfaces directly to a TDM
backplane. In this mode, each TDM port of the device is serviced by a common clock in both the input and output
directions. When operating in TDM backplane mode, the Clock Management module is responsible for the
generation of bidirectional clock and frame pulse signals. In order to support a variety of customer applications, the
clock can be running at either once or twice the TDM data rate.
When operating in backplane slave mode, the backplane clock signal and frame pulse are routed directly from the
external pins through the Clock Management module to the TDM bus module. Contrarily, when the MT90520 is
operating as the TDM backplane master, it is the responsibility of the Clock Management module to generate both
the clock and frame pulse signals. These signals are transmitted to external device pins as well as to the TDM bus
module.
As a secondary clock control function, the Clock Management module always provides a continuous TDM line rate
clock to the TDM bus module when operating in UDT mode. In the event of a Loss of Signal (LOS) condition, the
Clock Management module automatically routes the port’s internally-generated PLL clock to the TDM bus module if
the user has selected the port’s STiCLK as the source for SToCLK. The TDM bus module uses a user-
programmable configuration bit (TDM_LOS_CLK in the per-port TDM Control Register 1) to select either the
external input clock for the port or the port’s internally-generated PLL clock as the source of the TDM sampling
clock.
As a clock control function which permits clock recovery at the remote end, the Clock Management module
generates Residual Time Stamp (RTS) signals based on the relationship between the network clock and the local
bit-rate clock, on a per-port basis. In the segmentation direction, the RTS values are output to the TX_SAR header
generation module, where they are inserted into ATM cells for transmission to the remote end.
4.7.1.2 Clock Recovery
In order to meet the CES specification for SDT and UDT operation, the MT90520 provides synchronous, SRTS,
and adaptive clock recovery methods.
The MT90520 permits synchronous clock recovery in UDT, SDT, and TDM backplane modes. The MT90520
provides synchronous clock recovery via either an internal PLL or an external PLL. In order to comply with the CES
specification, the reference source for the optional external PLL must be traceable to a Primary Reference Source
(PRS). The user has the option of sourcing the external PLL from a network clock, clocks generated by the
MT90520’s internal PLLs, or TDM input clocks.
SRTS clock recovery is provided as outlined in U.S. Patent No. 5,260,978. Although the CES specification indicates
that SRTS is not required for SDT clock recovery, the MT90520 device permits the use of SRTS in the SDT mode of
operation when not operating in the CAS sub-mode. In the reassembly direction, RTS values extracted from
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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