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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 84/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
84
Zarlink Semiconductor Inc.
When the processing of CAS nibbles is enabled (i.e., the
CAS<0>
bit in the SDT Reassembly Control Structure for
a VC is set) the module first has to determine the location of the CAS nibbles within the received cells. In general,
data which is extracted from cells when the Current Frame is equal to the CAS frame (frame 16 in E1 mode; frame
24 in DS1 mode), is considered to be CAS. However, within the MT90520, extra checking routines are performed to
ensure that the data that is extracted from the received cells is really CAS, before it is treated as such. If there is
any doubt about the integrity of the CAS (e.g., Fast SN Processing state machine is not in sync; a pointer reframe is
pending), the received data is not processed as CAS. Instead, the CASx fields in the SDT Reassembly Control
Structure are not updated until the error conditions have been removed and there is confidence regarding the
alignment of TDM and CAS data with the correct TDM output channels. Another point should be made: the CASx
fields are only updated if the
CAS<1>
bit in the SDT Reassembly Control Structure for the VC is
cleared
, indicating
that the user wishes to use the received CAS nibbles, rather than user-defined signalling.
If all of the error-checking conditions outlined above are met, the extracted CAS nibble is written to the CASx field of
the SDT Reassembly Control Structure, corresponding to the Current Entry pointer. Note that strict multiframing is
not used in the MT90520 device, due to concern about delay. Although CAS and TDM data are meant to be
aligned, the MT90520 device would have to store up all of the data for an entire AAL1 structure (i.e., a complete
multiframe) if the TDM data was to be output simultaneously with the corresponding CAS data. The resultant delay
in the reception of data at the TDM ports is considered to be undesirable, so extra buffering of TDM data is not
performed. Instead, when all of the channels in the VC have had their corresponding CAS nibbles processed, the
Current Entry and Current Frame values wrap around. In the frame following that in which CAS data is received
(i.e., the first frame of the multiframe), the new CAS data is output to the TDM module. As well, the
MF
(multiframe)
bit is set in each SDT Reassembly Circular Buffer corresponding to the VC. This indicator is used by the TDM
module to align data with the SToMF signal on the TDM interface bus.
One other user-programmable option is possible with respect to the reception of CAS data. When a CAS nibble is
received and is considered valid, regardless of whether the user has decided to enable write-backs via the clearing
of CAS<1>, it is possible for an examination of the nibble to be performed. If the user sets
CAS<2>
, the received
nibble is compared to the previous CAS nibble for the channel (stored in CASx). If the nibble has changed, the
Cc
(CAS Changed)
bit of the VC’s SDT Reassembly Control Structure is set. User software could be configured to
read the VC’s CAS nibbles and monitor for changes when the Cc bit is set.
SDT Overflow and Underrun Detection
The SDT RX_SAR is responsible for generating buffer overflow and buffer underrun error notifications on a per-VC
basis. In addition to determining if errors occur, the SDT RX_SAR also attempts to compensate for these slips by
adjusting its write pointer. The goal of the write pointer adjustment is to prevent the occurrence of multiple
consecutive slips.
Upon start-up, the SDT RX_SAR write pointer is set to a pre-defined slip-pointer value, regardless of the current
relationship between the SDT RX_SAR write pointer and the TDM read pointer. Therefore, if no slips occur, the
write pointer should always be an “average” distance away from the TDM read pointer.
For all cells other than the first cell received on a VC, an algorithmic slip-checking routine is performed when the
cell is about to be written to the SDT Reassembly Circular Buffer(s). Each time a cell is to be written to external
memory, the algorithm looks at the relationship between the SDT RX_SAR’s write pointer and the controlling port’s
TDM module’s read pointer (the controlling port is determined by the setting of the
VC TDM Port
field). The
algorithm then determines whether the next write to occur will be an “okay” condition, an overflow, or an underrun.
Generally speaking, an “okay” condition means that the SDT RX_SAR is trying to write to a memory location which
is within a pre-defined distance (determined by Maximum Lead) from the TDM read pointer. Overflow conditions are
conditions in which there is a risk of the SDT RX_SAR over-writing data which has yet to be read by the TDM
module. Underruns occur when the TDM has begun to re-read data from the buffer because it has not been
replaced by new data from the SDT RX_SAR.
If an “okay” condition is detected, the SDT RX_SAR is permitted to write to the SDT Reassembly Circular Buffer(s)
at the location determined by the
SDT RX_SAR Write Pointer
and the
Reassembly Circular Buffer Base
Addresses
fields
from the VC’s SDT Reassembly Control Structure. In the case of a slip (either an underrun or an
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|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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