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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 89/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
89
Zarlink Semiconductor Inc.
in the buffer. The user can select (via the register at byte address 2024h) a buffer capable of holding 16, 32, 64, or
128 cells. Each cell is allocated 64 bytes in external memory.
A particular cell entry within the buffer is selected to be written to via the Data RX_SAR write pointer. The write
pointer can not be modified by the CPU; therefore, following the assertion of Data RX_SAR Enable, writes always
begin at cell location #0 within the buffer.
Received Data Cell Counter
The Data RX_SAR also provides the user with the number of data cells received from the UTOPIA block. This 16-
bit counter value can be viewed in register DRCCR at address 202Ah. This counter is incremented every time a
data cell is received from the UTOPIA. It is not reset when the Data RX_SAR is disabled. When this counter rolls
over, a status bit gets set in the DRSR register at address 2022h. This status bit can be cleared by software. This
rollover condition can also generate a service request to the CPU if the corresponding service enable bit is set in
the DRCR register at address 2020h.
4.6.3.2 Error Handling
In order to prevent the CPU from reading cell locations that have not yet been written, a register is provided to store
the value of the CPU’s read pointer. Upon start-up, this register is reset to point to the final cell location within the
buffer. In general, to prevent slip conditions, software should be designed to ensure that the CPU’s read pointer is
never pointing to a cell location pointed to by the Data RX_SAR write pointer. During a cell-write operation, the write
pointer indicates the cell location which is currently being written (the cell is not yet valid for reading). At the end of
the write process, the write pointer is incremented, pointing to the cell location which will be written with the next
received data cell. Contrarily, the CPU’s read pointer should be incremented at the beginning of a cell-read, to point
to the cell location that is
currently
being read. At the end of a cell-read, software should
not
increment the read
pointer.
The
Data RX_SAR Cell Arrival
status bit is provided to permit greater software control. This bit in the Data
RX_SAR Status Register (address 2022h) is set each time that a cell has been completely written into the Data
RX_SAR Cell Buffer. The bit signifies to the CPU that valid data has been written into the buffer. Software can clear
this status bit by performing a write of ‘0’ to the register bit location.
At the end of each cell-write cycle, a comparison is made between the CPU’s read pointer and the Data RX_SAR’s
write pointer. If the write pointer is at a distance of half the buffer size from the CPU’s read pointer, a buffer half full
condition is flagged by setting a status bit (
Data RX_SAR Buffer Half Full
) in the Data RX_SAR Status Register
(DRSR). Software can clear this bit by writing ‘0’ to the register bit location.
If a buffer half full condition is not detected, the CPU’s read pointer is compared to the Data RX_SAR’s write pointer.
If they are equal, an overrun condition is flagged by setting a status bit (
Data RX_SAR Cell Buffer Overrun Error
)
in the Data RX_SAR Status Register at address 2022h. This status bit can be cleared by performing a write of ‘0’ to
the register bit location. The overrun status bit may be interpreted by the user’s software in two possible ways:
If the CPU is in the middle of a read operation (i.e., it has started processing a cell in the buffer, but has not
read the entire cell), this flag signifies that a buffer overrun event has occurred - the Data RX_SAR has over-
written the cell location which is being read by the CPU. In this case, software should discard the portion of
the cell already read by the CPU and advance the read pointer so that it is pointing to a valid cell location.
On the other hand, if the CPU is not performing a read operation, the flag signifies that a buffer overrun is
about to occur. Specifically, an overrun could occur on the next cell-write. If the CPU does not read the
complete subsequent cell in the buffer before the next cell-write occurs, any data stored in that cell location
will be overwritten by the Data RX_SAR. As such, the next cell (which may or may not actually be
overwritten) should still be treated as corrupted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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