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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 81/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
81
Zarlink Semiconductor Inc.
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if the internal controller reaches the start of the AAL1 structure during the current cell, re-
synchronization occurs and the Pointer Reframes statistic field in the SDT Reassembly Control
Structure is incremented.
-
if the internal controller does not reach the start of the AAL1 structure during the current cell, the
P
(Pointer Reframe Pending)
bit of the SDT Reassembly Control Structure is set. Ultimately, when re-
synchronization does occur, the P status bit is cleared and the Pointer Reframes statistic field in the
SDT Reassembly Control Structure is incremented.
Note:
Even in normal operation, one pointer reframe will usually be reported on each SDT VC, shortly after start-
up. Because the first cell received on a VC is always discarded by the SDT Fast SN Processing state machine (as
per the ITU-T I.363.1 standard), the first available pointer is always discarded. Therefore, the SDT RX_SAR
processes a minimum of 7 cells before another pointer is received. Thus, the data for the first 8-cell sequence is
generally misaligned and directed toward the wrong TDM channels. When the second pointer is received, the
internal location controller is adjusted to the value contained in the received pointer byte and, in most cases, a
pointer reframe is reported.
SDT Reassembly Circular Buffers
In the SDT mode of operation, TDM data is processed on a per-channel basis, rather than on a per-VC basis, as in
the UDT case. As a result, when operating in SDT mode, each channel within a VC is allocated its own SDT
Reassembly Circular Buffer in external memory.
SDT Reassembly Circular Buffers have programmable lengths (on a per-VC basis). The user may configure a VC
such that the buffers associated with the VC have lengths of 64, 128, 256, 512, or 1024 entries, based on the
configuration of the
BS
(Buffer Size)
bits in the SDT Reassembly Control Structure for the VC. Note that all of the
buffers for a particular VC have the same size. The size of buffers selected should be influenced by the expected
CDV on a VC. For instance, if a large CDV is expected, a longer buffer would be desirable, so that there is sufficient
data to play out to the TDM bus in the period between cell arrivals.
The user can adjust the
Maximum Lead
field in the VC’s SDT Reassembly Control Structure to provide further
control over the CDV tolerance of the VC. The Maximum Lead field, as outlined in “SDT Reassembly Control
Structures” on page 68, is user-programmable and determines the maximum distance between the TDM module’s
read pointer and the SDT RX_SAR’s write pointer. In general, Maximum Lead should be set to a value which, when
used in combination with Buffer Size, will result in the desired CDV buffering. The setting of Maximum Lead
effectively shortens the buffer length, ensuring that there is no excessive delay between the time that data is
received at the buffer input and when it is played out on the TDM output bus. However, if Maximum Lead is not set
in accordance with the CDV of the incoming cells, it can result in the reporting of slips (underruns or overflows),
which may cause data received at the SDT Reassembly Circular Buffers to be overwritten or skipped. In general,
Maximum Lead should be set to a value calculated as follows:
Maximum Lead in bytes = desired buffer limit in bytes = 2 + (2 * CDV) / 0.125 ms, where CDV is in
milliseconds
.
Because there is no pre-defined mapping for the SDT Reassembly Circular Buffers, they can be programmed to
start anywhere in the external memory for the MT90520 device (with some restrictions, explained here). The
address of each SDT Reassembly Circular Buffer is formed as follows. A two-bit value is obtained from the
CB_BASE_ADD
field of the SDT Reassembly Control Register at byte-address 2040h. These bits form the two
most significant bits of the address to external memory. The complete address is formed by concatenating these
bits with the 12-bit value obtained from a
Reassembly Circular Buffer Base Address
field within each SDT
Reassembly Control Structure.
The number of bits of the concatenated (i.e., 14-bit) address which are used to form the actual address to external
memory is determined by the size of the buffers selected for the VC. For instance, if 64-entry buffers are selected,
all 14 bits of the concatenated address are used. However, if 1024-entry buffers are selected, only the bottom 10
bits of the address are used. Refer to Table 18 below for more details regarding how the base addresses of the
SDT Reassembly Circular Buffers are formed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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