參數(shù)資料
型號： MT55L1MY18P
廠商： Micron Technology, Inc.
英文描述： 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器)
中文描述： 16Mb的：1梅格× 18，流量通過ZBT SRAM的（16Mb的流通式同步靜態(tài)存儲器）
文件頁數(shù)： 19/34頁
文件大?。?/td> 460K
代理商： MT55L1MY18P
19
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
NOTE:
1. Measured as HIGH above V
IH
and LOW below V
IL
.
2. Refer to Technical Note TN-55-01, “ Designing with ZBT SRAMs,” for a more thorough discussion of these parameters.
3. This parameter is sampled.
4. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
5. Transition is measured ±200mV from steady state voltage.
6. OE# can be considered a “ Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
8. Test conditions as specified with output loading as shown in Figure 1 for 3.3V I/O (V
DD
Q = +3.3V ±0.165V) and
Figure 3 for 2.5V I/O (V
DD
Q = +2.5V +0.4V/-0.125V).
9. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
10. If V
DD
= +3.3V, then V
DD
Q = +3.3V or +2.5V. If V
DD
= +2.5V, then V
DD
Q = +2.5V.
Voltage tolerances: +3.3V ±0.165 or +2.5V ±0.125V for all values of V
DD
and V
DD
Q.
AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9, 10) (0oC
￡
T
A
￡
+70oC)
-6
-7.5
-10
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
t
KHKH
f
KF
t
KHKL
t
KLKH
6.0
7.5
10
ns
166
133
100
MHz
ns
ns
1.8
1.8
2.2
2.2
3.2
3.2
1
1
t
KHQV
t
KHQX
t
KHQX1
t
KHQZ
t
GLQV
t
GLQX
t
GHQZ
3.5
4.2
5.0
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
2, 3, 4, 5
2, 3, 4, 5
6
2, 3, 4, 5
2, 3, 4, 5
3.0
3.5
3.0
4.2
3.3
5.0
0
0
0
3.5
4.2
5.0
t
AVKH
t
EVKH
t
CVKH
t
DVKH
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
ns
ns
ns
ns
7
7
7
7
t
KHAX
t
KHEX
t
KHCX
t
KHDX
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
7
7
7
7
相關(guān)PDF資料
PDF描述
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