
15
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
3.3V V
DD
, ABSOLUTE MAXIMUM
RATINGS*
Voltage on V
DD
Supply Relative
to V
SS
............................................... -0.5V to +4.6V
Voltage on V
DD
Q Supply Relative
to V
SS
...................................................-0.5V to V
DD
V
IN
.............................................. -0.5V to V
DD
Q + 0.5V
Storage Temperature (TQFP) .............. -55oC to +150oC
Storage Temperature (FBGA) ............. -55oC to +125oC
Junction Temperature**................................... +150oC
Short Circuit Output Current ...........................100mA
2.5V V
DD
, ABSOLUTE MAXIMUM
RATINGS*
Voltage on V
DD
Supply Relative
to V
SS
............................................... -0.3V to +3.6V
Voltage on V
DD
Q Supply Relative
to V
SS
................................................-0.3V to +3.6V
V
IN
.............................................. -0.3V to V
DD
Q + 0.3V
Storage Temperature (plastic) ............ -55oC to +150oC
Storage Temperature (FBGA) ............. -55oC to +125oC
Junction Temperature**................................... +150oC
Short Circuit Output Current ...........................100mA
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Junction temperature depends upon package type,
cycle time, loading, ambient temperature and airflow.
See Micron Technical Note TN-05-14 for more
information.
3.3V V
DD
, 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0oC
£
T
A
£
+70oC; V
DD
= +3.3V ±0.165V, V
DD
Q = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
CONDITIONS
SYMBOL
V
IH
V
IH
V
IL
IL
I
IL
O
MIN
2.0
2.0
-0.3
-1.0
-1.0
MAX
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.0
1.0
UNITS
V
V
V
μA
μA
NOTES
1, 2
1, 2
1, 2
3, 6
DQ pins
0V
£
V
IN
£
V
DD
Output(s) disabled,
0V
£
V
IN
£
V
DD
I
OH
= -4.0mA
I
OL
= 8.0mA
Output High Voltage
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
V
OH
V
OL
V
DD
V
DD
Q
2.4
–
3.135
3.135
–
V
V
V
V
1, 4
1, 4
1
1, 5
0.4
3.465
V
DD
NOTE:
1. All voltages referenced to V
SS
(GND).
2. For 3.3V V
DD
:
Overshoot:
Undershoot:
Power-up:
For 2.5V V
DD
:
Overshoot:
Undershoot:
Power-up:
3. MODE pin has an internal pull-up, and input leakage = ±10μA.
4. The load used for V
OH
, V
OL
testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O
curves are available upon request.
5. V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q can be externally wired together to the same power supply.
6. Ms# pin has an internal pull-down , and input leakage = ±10μA.
V
IH
£
+4.6V for t
£
t
KC/2 for I
£
20mA
V
IL
3
-0.7V for t
£
t
KC/2 for I
£
20mA
V
IH
£
+3.6V and V
DD
£
3.135V for t
£
200ms
V
IH
£
+3.6V for t
£
t
KC/2 for I
£
20mA
V
IL
3
-0.5V for t
£
t
KC/2 for I
£
20mA
V
IH
£
+2.65V and V
DD
£
2.375V for t
£
200ms