
353
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
causing the setting of the Interrupt Flag. The Output Compare pin is changed on the
timer clock and is not synchronized to the processor clock.
If the CPU wakes up from asynchronous timer and goes back to sleep again, it may
wakeup multiple times or the IRQ is called multiple times. This may be avoided if the
CPU waits with the next sleep instruction until the next asynchronous clock arrives.
21.10 Timer/Counter Prescaler
Figure 21-12. Prescaler for Timer/Counter2
The register ASSR defines the clock source for the asynchronous Timer/Counter2. The
clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the
main system I/O clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is
asynchronously clocked either from the TOSC1 or from the AMR pin. This enables the
use of Timer/Counter2 as a Real Time Counter (RTC).
The TOSC1 pin is selected by setting the EXCLKAMR bit in the ASSR register to logic
zero. Under this condition TOSC1 and TOSC2 are disconnected from Port G and a
crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an
independent clock source for Timer/Counter2. The Oscillator is optimized for use with a
32.768 kHz crystal. By setting the EXCLK bit in the ASSR, a 32 kHz external clock can
be applied on TOSC1.
Setting the EXCLKAMR bit to logic one selects the AMR pin as the Timer/Counter2
clock source. Thus the 32 kHz oscillator can be used by the MAC symbol counter while
A complete overview of the implemented asynchronous clock sources can be found in
For Timer/Counter2, the possible pre-scaled selections are: clkT2S/8, clkT2S/32, clkT2S
/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may
be selected. Setting the PSRASY bit in GTCCR resets the prescaler. This allows the
user to operate with a predictable prescaler.