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型號(hào)：	MQ80C52TXXX-20/883D
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	193/604頁(yè)
文件大小：	22337K
代理商：	MQ80C52TXXX-20/883D

42073A-MCU Wireless-02/13

ATmega2564/1284/644RFR2

17.9.6 OCR0B – Timer/Counter0 Output Compare Register B

Initial Value

Initial Value

The Output Compare Register B contains an 8-bit value that is continuously compared

with the counter value (TCNT0). A match can be used to generate an Output Compare

interrupt, or to generate a waveform output on the OC0B pin.

Bit 7:0 – OCR0B_7:0 - Output Compare Register

17.9.7 TIMSK0 – Timer/Counter0 Interrupt Mask Register

Initial Value

Bit 7:3 – Res4:0 - Reserved

This bit is reserved for future use. A read access always will return zero. A write access

does not modify the content.

Bit 2 – OCIE0B - Timer/Counter0 Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match B interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0B bit is set

in the Timer/Counter0 Interrupt Flag Register TIFR0.

Bit 1 – OCIE0A - Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set

in the Timer/Counter0 Interrupt Flag Register TIFR0.

Bit 0 – TOIE0 - Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed

if an overflow in Timer/Counter0 occurs i.e., when the TOV0 bit is set in the

Timer/Counter0 Interrupt Flag Register TIFR0.

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MQ82380-20/R	制造商:Rochester Electronics LLC 功能描述:
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