
159
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
The Symbol Counter together with the three compare units provide support for waking
up the device at the right time to receive the beacon for superframe synchronization
and at certain times within the superframe.
A typical superframe timing scenario using the symbol counter relative compare mode
realistic time intervals but demonstrate the principle of operation.
Figure 10-3. Relative Compare Mode
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The compare match registers are programmed with symbol intervals relative to the
beacon frame SFD timestamp. For instance the SCCMP1 is programmed to 80,
because the first Granted Time Slot (GTS1) is expected 80 symbols after the beacon
frame. Register SCCMP2 is programmed to 156 to meet GTS3 156 symbols after the
beacon frame. SCCMP3 is programmed to 312. This is the time interval where the
beacon of the next superframe is expected. Because it requires some time to activate
the transceiver and there is also some timing drift possible, the compare interrupt must
be programmed to wake up some symbols in advance to make sure the next beacon is
not missed.
If the controller receives a compare match wake up event it is activating the transceiver.
After the frame operations are finished, the system can go back to sleep until the next
compare match event occurs.
10.11 Register Description
10.11.1 SCCSR – Symbol Counter Compare Source Register
Bit
7
6
5
4
3
2
1
0
NA ($DB)
Res1
Res0
SCCS31
SCCS30
SCCS21
SCCS20
SCCS11
SCCS10
SCCSR
Read/Write
R
RW
Initial Value
0