
20
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
Figure 8-8. On-Chip Data SRAM Access Cycles
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
8.3 EEPROM Data Memory
The ATmega2564/1284/644RFR2 contains EEPROM_SIZE Bytes of data EEPROM
memory. It is organized as a separate data space. Read access is byte-wise. The
access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control
Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
8.3.1 EEPROM Read Write Access
The EEPROM Access Registers are accessible in the I/O space, see
"EEPROMfunction, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, DVDD is likely to rise or fall slowly on power-
up/down. This causes the device for some period of time to run at a voltage lower than
In order to prevent unintentional EEPROM writes, a specific write procedure must be
followed. See the description of the EEPROM Control Register for details on this,
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The calibrated oscillator is used to time the EEPROM accesses. The following table
lists the typical programming time for EEPROM access from the CPU.
Table 8-3. EEPROM Programming Time
Symbol
Typical Programming time
EEPROM write (from CPU)
4.5 ms
EEPROM erase (from CPU)
8.5 ms