
152
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
9.12.71 MAFSA3L – Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
Bit
7
6
5
4
3
2
1
0
NA ($11A)
MAFSA3L7:0
MAFSA3L
Read/Write
RW
Initial Value
1
This register contains the lower 8 bits of the MAC short address for Frame Filter 3
address recognition.
Bit 7:0 – MAFSA3L7:0 - MAC Short Address low Byte for Frame Filter 3
These bits contain the bits [7:0] of the MAC short address for Frame Filter 3.
9.12.72 TST_CTRL_DIGI – Transceiver Digital Test Control Register
Bit
7
6
NA ($176)
TST_CTRL_DIG_7
TST_CTRL_DIG_6
TST_CTRL_DIGI
Read/Write
RW
Initial Value
0
Bit
5
4
NA ($176)
TST_CTRL_DIG_5
TST_CTRL_DIG_4
TST_CTRL_DIGI
Read/Write
RW
Initial Value
0
Bit
3
2
NA ($176)
TST_CTRL_DIG3
TST_CTRL_DIG2
TST_CTRL_DIGI
Read/Write
RW
Initial Value
0
Bit
1
0
NA ($176)
TST_CTRL_DIG1
TST_CTRL_DIG0
TST_CTRL_DIGI
Read/Write
RW
Initial Value
0
This register takes part in the activation sequence of the continuous transmission test
mode. Other functionality of this register is reserved for internal use.
Bit 7 – TST_CTRL_DIG_7 - Disable Receiver Baseband Frequency Synthesis
This bit is reserved for internal use. It is used to switch the frequency synthesis of the
receiver baseband path. A value of 0 switches the synthesis on. A value of 1 switches
the synthesis off.
Bit 6 – TST_CTRL_DIG_6 - Disable Receiver Baseband Drift Compensation
This bit is reserved for internal use. It is used to switch the drift compensation of the
receiver baseband path. A value of 0 switches the compensation on. A value of 1
switches the compensation off.
Bit 5 – TST_CTRL_DIG_5 - Enable Switch of Transceiver FIFO
This bit is reserved for internal use. It is used enable a bypass for TX/RX FIFO buffers.
A frame transmit will be write the TX FIFO data directly into the RX FIFO data field with
the same address. This test can be used for the RX/TX FIFO test. A value of 0 disables
the bypass. A value of 1 enables the bypass.