
158
42073A-MCU Wireless-02/13
ATmega2564/1284/644RFR2
All Interrupts can be used to wakeup the controller from any sleep state.
10.9 Backoff Slot Counter
The backoff slot counter can be used to provide accurate MAC protocol timing. The
counter is sourced by the transceiver clock and works only if the transceiver clock is
running. If the transceiver is disabled or in sleep mode the counter is also disabled.
The counter generates periodic Interrupts every 20 symbols, i.e. every 320 s.
10.10 Symbol Counter Usage
10.10.1 SFD and Beacon Timestamp Generation
The SFD timestamp register is updated with the symbol counter value at the time the
SFD value has been received completely. For an incoming frame, the register is valid
after the RX_START IRQ was issued until the next RX_START IRQ. SFD timestamps
are generated for all incoming frames with valid SFD and length field even if the PSDU
is corrupted (invalid FCS).
Figure 10-2. SFD and Beacon Timestamp Generation
Note that Figure 10-2 contains no exact timing information; it is for visualization only.
The beacon timestamp register is updated with the SFD timestamp value at the end of
the frame (RX_END IRQ), if the received frame was a beacon frame with valid FCS and
expected source PAN identifier or { PAN_ID_1, PAN_ID_0} = 0xFFFF.
The register value is valid until a new beacon frame has been received or the beacon
timestamp is updated manually. A manual beacon timestamp can be generated by
writing “1” to SCMBTS of the SCCR0 register.
10.10.2 Relative Compare Mode for Superframe Access Timing
The IEEE 802.15.4 describes a superframe structure which contains different time slots
where a device can access the channel.