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參數(shù)資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MPC9894VFR2 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
15
MPC9894
Output Power-Up Register
The Output Power-Up Register configures each of the 8
LVPECL outputs for either power-up or a power-down state.
The use of these bits allows power consumption to be
reduced when all of the clock outputs are not used. Placing
an output in the power-down condition is not synchronous
with the clock edges.
Feedback Power-Up Register
The Feedback Power-Up register bit 0 is used to configure
the MPC9894 feedback output in either a power-up state or a
power-down state. Note this register bit is valid for internal
feedback configuration only. When external feedback is
selected QFB is always enabled and in a power-up state. The
remaining bits of this register are unused and read as a
logic 0.
Table 25. Output Power-Up Register (Register 6 — Read/Write)
Bit
76543
2
1
0
Description
PWR_QD1
PWR_QD0
PWR_QC1
PWR_QC0
PWR_QB1
PWR_QB01
PWR_QA1
PWR_QA0
Reset Default
00000
0
Preset Default
11111
1
Table 26. Clock Output Power-Up Bits
PWR_Qxx
Description
0
Output Power-Down
1
Output Power-Up
Table 27. Feedback Power-Up Register (Register 7 — Read/Write)
Bit
7
6
5
432
1
0
Description
PWR_QFB
Reset Default
0
Preset Default
1
Table 28. Feedback Output Power-Up Bit
PWR_QFB
Description
0
Feedback Output Power-Down
1
Feedback Output Power-Up
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