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參數(shù)資料
| 型號(hào)： | MPC9894VFR2 |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁(yè)數(shù)： | 23/28頁(yè) |
| 文件大?。?/td> | 362K |
| 代理商： | MPC9894VFR2 |
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Advanced Clock Drivers Devices
4
Freescale Semiconductor
MPC9894
Table 2. Function Table
Control
Default
0
1
Control Inputs
PLL_BYPASS
0
PLL enabled. The input to output frequency
relationship is according to Table 9 if the PLL is
frequency locked.
PLL bypassed and IDCS disabled. The VCO output is
replaced by the reference clock signal fREF. This is
considered to be a test mode and clock monitoring and
clock switching are disabled during this operation.
CLK_VALID[3:0]
0
The associated clock input is considered to be invalid
and usable
The associated clock input is considered to be a valid
usable clock input
CLK_ALARM_RST
1
CLK_STAT[3:0] and SEL_STAT[1:0] flags are reset:
CLK_STAT[3:0] = 0000 and SEL_STAT[1:0] = 00.
CLK_ALARM_RST is a one-shot function.
CLK_STAT[3:0] and SEL_STAT[1:0] flags are active
MR
1
Reset of data generators and output dividers. The
MPC9894 requires reset at power-up and after any
loss of PLL lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length of the
reset pulse should be greater than two reference clock
cycles
Outputs enabled (active)
MBOOT
0
I2C read/write mode
I2C boot mode
PRESET
0
Normal Operation
Uses Configuration Register PRESET values on MR
EX_FB_SEL
0
Selects internal feedback path
Selects external feedback path
MEDIA
0
Low output impedance (QA0 to QD1 and QFB)
50
output impedance (QA0 to QD1 and QFB)
SEL_2P5V
0
Selects 3.3 V for core VDD
Selects 2.5 V for core VDD
MSTROUT_EN
All outputs disabled (synchronous with clock being low) All outputs enabled
Control Outputs
LOCK(1)
PLL is locked
PLL is unlocked
BUSY(1)
The IDCS has initiated a clock switch.
No clock switch currently performed
INT
IDCS status has changed (indicates an assertion of
CLK_STAT[3:0] or deassertion of LOCK)
No status change
CLK_STAT[3:0]
Associated clock input not valid
Associated clock input valid
SEL_STAT[1:0]
Encoded value refer to Table 7
1. The combined pins of LOCK = 1 and BUSY = 0 are used to indicate a catastrophic failure. Refer to PLL Out-of-Lock Conditions.
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