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參數(shù)資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 362K |
| 代理商： | MPC9894VFR2 |
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Advanced Clock Drivers Devices
22
Freescale Semiconductor
MPC9894
MPC9894 Pin and Package
Table 40. MPC9894 Pin Listing
Signal Name
Description
Direction
Type
Active State
Supply
Pin
CLK0
Clock0 Positive Input
Input
LVPECL
—
VDDIC
D1
CLK0
Clock0 Negative Input
Input
LVPECL
—
VDDIC
D2
CLK1
Clock1 Positive Input
Input
LVPECL
—
VDDIC
E3
CLK1
Clock1 Negative Input
Input
LVPECL
—
VDDIC
E2
CLK2
Clock2 Positive Input
Input
LVPECL
—
VDDIC
F3
CLK2
Clock2 Negative Input
Input
LVPECL
—
VDDIC
F2
CLK3
Clock3 Positive Input
Input
LVPECL
—
VDDIC
G1
CLK3
Clock3 Negative Input
Input
LVPECL
—
VDDIC
G2
FB_IN
Feedback Clock Positive Input
Input
LVPECL
—
VDDIC
C1
FB_IN
Feedback Clock Negative Input
Input
LVPECL
—
VDDIC
C2
QA0
Positive Differential Clock Output
Output
LVPECL
—
VDDAB
K4
QA0
Negative Differential Clock Output
Output
LVPECL
—
VDDAB
J4
QA1
Positive Differential Clock Output
Output
LVPECL
—
VDDAB
K5
QA1
Negative Differential Clock Output
Output
LVPECL
—
VDDAB
J5
QB0
Positive Differential Clock Output
Output
LVPECL
—
VDDAB
K7
QB0
Negative Differential Clock Output
Output
LVPECL
—
VDDAB
J7
QB1
Positive Differential Clock Output
Output
LVPECL
—
VDDAB
K6
QB1
Negative Differential Clock Output
Output
LVPECL
—
VDDAB
J6
QC0
Positive Differential Clock Output
Output
LVPECL
—
VDDCD
A7
QC0
Negative Differential Clock Output
Output
LVPECL
—
VDDCD
B7
QC1
Positive Differential Clock Output
Output
LVPECL
—
VDDCD
A6
QC1
Negative Differential Clock Output
Output
LVPECL
—
VDDCD
B6
QD0
Positive Differential Clock Output
Output
LVPECL
—
VDDCD
A4
QD0
Negative Differential Clock Output
Output
LVPECL
—
VDDCD
B4
QD1
Positive Differential Clock Output
Output
LVPECL
—
VDDCD
A5
QD1
Negative Differential Clock Output
Output
LVPECL
—
VDDCD
B5
QFB
Positive Differential Clock Output
Output
LVPECL
—
VDDCD
A3
QFB
Negative Differential Clock Output
Output
LVPECL
—
VDDCD
B3
CLK_VALID3
Qualifier for clock input CLK3
Input
LVCMOS
High
VDD
F10
CLK_VALID2
Qualifier for clock input CLK2
Input
LVCMOS
High
VDD
E10
CLK_VALID1
Qualifier for clock input CLK1
Input
LVCMOS
High
VDD
E9
CLK_VALID0
Qualifier for clock input CLK0
Input
LVCMOS
High
VDD
E8
CLK_ALARM_RST Reset of all four alarm status flags and clock
selection status flag
Input
LVCMOS
Low
VDD
F8
PLL_BYPASS
Select PLL of static test mode
Input
LVCMOS
High
VDD
F9
MEDIA
Output impedance control (high = 50
)
Input
LVCMOS
High
VDD
E7
SCL
I2C Interface Control, Clock
I/O
LVCMOS
—
VDD
C9
SDA
I2C Interface Control, Data
I/O
LVCMOS
—
VDD
C10
ADDR2
I2C Interface Control, Address 2 (MSB)
Input
LVCMOS
—
VDD
A9
ADDR1
I2C Interface Control, Address 1
Input
—
VDD
B8
ADDR0
I2C Interface Control, Address 1 (LSB)
Input
LVCMOS
—
VDD
A8
MR
Device Master Reset
Input
LVCMOS
Low
VDD
D10
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