- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26839 > MPC9894VFR2 (INTEGRATED DEVICE TECHNOLOGY INC) 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 PDF資料下載
參數(shù)資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MPC9894VFR2 |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Advanced Clock Drivers Devices
10
Freescale Semiconductor
MPC9894
INPUT AND OUTPUT FREQUENCY CONFIGURATION
Configuring the MPC9894 input and output frequencies
requires programming the internal PLL input, feedback and
output dividers. The output frequency is represented by the
following formula:
fOUT =[(fREF ÷ P) M] ÷ N
where fREF is the reference frequency of the selected input
clock source (reference input), M is the PLL feedback divider
and N is an output divider. The PLL input divider P, the
feedback divider M and the output divider are configured by
the device registers 1 and 4. The MPC9894 has four output
banks (Bank A, B, C, and D) and each output bank can be
configured individually as shown in Table 8.
The reference frequency fREF and the selection of the PLL
input divider (P) and feedback-divider (M) is limited by the
specified VCO frequency range. fREF, P and M must be
configured to match the VCO frequency range of 340 to
680 MHz in order to achieve stable PLL operation:
fVCO,MIN ≤ (fREF ÷ P M) ≤ fVCO,MAX
The PLL input divider (P) can be used to situate the VCO
in the specified frequency range. The PLL input divider
effectively extends the usable input frequency range.
The output frequency for each bank can be derived from
the VCO frequency and output divider (N):
fQA[1:0] = fVCO ÷ NA
fQB[1:0] = fVCO ÷ NB
fQC[1:0] = fVCO ÷ NC
fQD[1:0] = fVCO ÷ ND
Table 9 illustrates the possible input clock frequency
configurations of the MPC9894. Note that the VCO lock
range is always 340 MHz to 680 MHz, setting lower and
upper boundaries for the frequency range of the device.
Figure 3. PLL Frequency Calculation
÷M
÷N
fREF
fOUT
÷P
PLL
Table 8. Configuration of PLL P, M and N Frequency Dividers
Divider
Available Values
Configuration Through
PLL Input Divider (P)
÷1, ÷2, ÷3, ÷4, ÷6
Input_FB_Div[3:0], Register 4, bit 3:0
PLL Feedback Divider (M)
÷8, ÷12, ÷16
PLL Output Divider, Bank A (NA)
÷2, ÷4, ÷8, ÷16
FSEL_B[1:0], Register 1, bit 7:6
PLL Output Divider, Bank B (NB)
÷2, ÷4, ÷8, ÷16
FSEL_B[1:0], Register 1, bit 5:4
PLL Output Divider, Bank C (NC)
÷2, ÷4, ÷8, ÷16
FSEL_C[1:0], Register 1, bit 3:2
PLL Output Divider, Bank D (ND)
÷2, ÷4, ÷8, ÷16
FSEL_D[1:0], Register 1, bit 1:0
Table 9. Input and Output Frequency Ranges
Input_FB_Div[3:0]
P
M
fREF range
MHz
Output frequency for any bank A, B, C or D (FSEL_x) and ratio to fREF
N=2
N =4
N=8
N =16
0
÷1
÷16
21.25 – 42.5
8
fREF
4
fREF
2
fREF
1
÷1
÷12
28.33 – 56.67
6
fREF
3
fREF
1.5
fREF
0.75
fREF
2
÷2
÷12
56.66 – 113.34
3
fREF
1.5
fREF
0.75
fREF
0.375
fREF
3
÷1
÷8
42.5 – 85.0
4
fREF
2
fREF
1
fREF
0.5
fREF
4
÷2
÷16
42.5 – 85.0
4
fREF
2
fREF
1
fREF
0.5
fREF
5
reserved
6
÷2
÷8
85.0 – 170.0
2
fREF
1
fREF
0.5
fREF
0.125
fREF
7
÷3
÷12
85.0 – 170.0
2
fREF
1
fREF
0.5
fREF
0.125
fREF
8
÷4
÷16
85.0 – 170.0
2
fREF
1
fREF
0.5
fREF
0.125
fREF
9
reserved
10
÷4
÷12
113.32 – 226.64
1.5
fREF
0.75
fREF
0.375
fREF
0.1875
fREF
11
reserved
12
reserved
13
reserved
14
4
÷8
170.0 – 340.0
1
fREF
0.5
fREF
0.25
fREF
0.125
fREF
15
6
÷12
170.0 – 340.0
1
fREF
0.5
fREF
0.25
fREF
0.125
fREF
相關PDF資料 |
PDF描述 |
|---|---|
| MPC998FAR2 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC998FA | 998 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9990FAR2 | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| MPC9991FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC99J93FAR2 | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9894VM | 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL |
| MPC990 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC990F18 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC991 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC991FA | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。