參數(shù)資料
型號： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁數(shù)： 6/58頁
文件大小： 596K
代理商： MPC8240LZU200X
14
MPC8240 Integrated Processor Hardware Specications
Electrical and Thermal Characteristics
1.4.2.3 Input AC Timing Specications
Table 8 provides the input AC timing specications. See Figure 6 and Figure 7.
Notes:
1
All memory and related interface input signal specications are measured from the TTL level (0.8 or 2.0
V) of the signal in question to the VM = 1.4 V of the rising edge of the memory bus clock,
SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the fre-
quency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of
PCI_SYNC_IN). See Figure 6.
2
All PCI signals are measured from OVdd/2 of the rising edge of PCI_SYNC_IN to 0.4*OVdd of the sig-
nal in question for 3.3 V PCI signaling levels. See Figure 7.
3
Input timings are measured at the pin.
4tCLK is the time of one SDRAM_SYNC_IN clock cycle.
5
All mode select input signals specications are measured from the TTL level (0.8 or 2.0 V) of the signal in
question to the VM = 1.4 V of the rising edge of the HRST_CPU / HRST_CTRL signal. See Figure 8.
.
Figure 6. Input-Output Timing Diagram Referenced to SDRAM_SYNC_IN
Table 8. Input AC Timing Specifications
At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3 V
Num
Characteristic
Min
Max
Units
Notes
10a
PCI input signals valid to PCI_SYNC_IN (input setup)
2.0
—
ns
2,3
10b1 Memory control and data input signals in ow through mode
valid to SDRAM_SYNC_IN (input setup)
3.0
—
ns
1,3
10b2 Memory control and data input signals in registered/in-line mode
valid to SDRAM_SYNC_IN (input setup)
2.5
—
ns
1,3
10b3 Memory control and data signals accessing non-dram valid to
SDRAM_SYNC_IN (input setup)
3.0
—
ns
1,3
10c
EPIC, misc. debug input signals valid to SDRAM_SYNC_IN
(input setup)
3.0
—
ns
1,3
10d
I2C input signals valid to SDRAM_SYNC_IN (input setup)
2.0
—
ns
1,3
10e
Mode select Inputs Valid to HRST_CPU / HRST_CTRL (input setup)
9*tCLK
—
ns
1,3–5
11a
PCI_SYNC_IN (SDRAM_SYNC_IN) to inputs invalid (input hold)
1.0
—
ns
1,2,3
11b
HRST_CPU / HRST_CTRL to mode select inputs invalid (input hold)
0
—
ns
1,3,5
11a
VM
VM = Midpoint Voltage (1.4V)
MEMORY
10b-d
PCI_SYNC_IN
INPUTS/OUTPUTS
13b
14b
VM
SDRAM_SYNC_IN
shown in 2:1 mode
Input Timing
Output Timing
12b-d
2.0 V
0.8 V
2.0 V
VM
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