參數(shù)資料
型號(hào)： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 2/58頁(yè)
文件大?。?/td> 596K
代理商： MPC8240LZU200X
10
MPC8240 Integrated Processor Hardware Specications
Electrical and Thermal Characteristics
1.4.1.5 Power Characteristics
Table 5 provides power consumption data for the MPC8240.
Table 5. Preliminary Power Consumption
Mode
PCI Bus Clock / Memory Bus Clock
CPU Clock Frequency (MHz)
Units
Notes
33/66/
166
33/66/
200
33/66/
233
33/83/
250
33/100
/
200
33/100
/
250
66/100
/
200
66/100
/
250
Typical
2.5
2.8
3.2
3.4
3.0
3.5
3.0
3.6
W
1, 5
Max - FP
3.0
3.4
3.8
4.1
3.6
4.2
3.6
4.3
W
1, 2
Max - INT
2.7
3.0
3.4
3.7
3.3
3.8
3.4
3.8
W
1, 3
Doze
1.8
2.0
2.2
2.4
2.2
2.6
2.2
2.6
W
1, 4, 6
Nap
700
800
900
mW
1, 4, 6
Sleep
500
800
mW
1, 4, 6
I/O Power Supplies
Mode
Minimum
Maximum
Units
Notes
Typ - OVdd
200
600
mW
7,8
Typ - GVdd
300
900
mW
7,9
Notes:
1
The values include Vdd, AVdd, AVdd2, and LAVdd but do not include I/O supply power, see
Section 1.7.3, “Power Supply Sizing,” for information on OVdd and GVdd supply power. One DIMM
used for memory loading.
2
Maximum - FP power is measured at Vdd = 2.625V with dynamic power management enabled while
running an entirely cache-resident, looping, oating point multiplication instruction.
3
Maximum - INT power is measured at Vdd = 2.625V with dynamic power management enabled while
running entirely cache-resident, looping, integer instructions.
4
Power saving mode maximums are measured at Vdd = 2.625V while the device is in doze, nap, or
sleep mode.
5
Typical power is measured at Vdd = AVdd = 2.5V, OVdd = 3.3V where a nominal FP value, a nominal
INT value, and a value where there is a continuous ush of cache lines with alternating ones and
zeroes on 64 bit boundaries to local memory are averaged.
6
Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7
The typical minimum I/O power values were results of the MPC8240 performing cache resident integer
operations at the slowest frequency combination of 33:66:166 (PCI:Mem:CPU) MHz.
8
The typical maximum OVdd value resulted from the MPC8240 operating at the fastest frequency com-
bination of 66:100:250 (PCI:Mem:CPU) MHz and performing continuous ushes of cache lines with
alternating ones and zeroes to PCI memory.
9
The typical maximum GVdd value resulted from the MPC8240 operating at the fastest frequency com-
bination of 66:100:250 (PCI:Mem:CPU) MHz and performing continuous ushes of cache lines with
alternating ones and zeroes on 64 bit boundaries to local memory.
10 Power consumption on the PLL supply pins (AVdd and AVdd2) and the DLL supply pin (LAVdd) less
than15 mW. This parameter is guaranteed by design and is not tested.
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