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參數(shù)資料
| 型號： | MPC8240LZU200X |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352 |
| 文件頁數(shù)： | 55/58頁 |
| 文件大?。?/td> | 596K |
| 代理商： | MPC8240LZU200X |
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6
MPC8240 Integrated Processor Hardware Specications
Electrical and Thermal Characteristics
1.4.1.2 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8240.
Table 2. Recommended Operating Conditions1
Characteristic
Symbol
Recommended
Value
Unit
Notes
Supply voltage
Vdd
2.5
± 5%
V
4,6
Supply voltage for PCI and standard bus
standards
OVdd
3.3
± 0.3
V
6
Supply voltages for memory bus drivers
GVdd
3.3
± 5%
V
8
PLL supply voltage - CPU core logic
AVdd
2.5
± 5%
V
4,6
PLL supply voltage - peripheral logic
AVdd2
2.5
± 5%
V
4,7
DLL supply voltage
LAVdd
2.5
± 5%
V
4,7
PCI reference
LVdd
5.0
± 5%
V
9,10
3.3
± 0.3
V
9,10
Input voltage
LVdd input tolerant
signals
VIN
0 to 3.6 or 5.75
V
2,3
All other inputs
0 to 3.6
V
5
Die-junction temperature
TJ
0 to 105
°C
Notes:
1
These are the recommended and tested operating conditions. Proper device
operation outside of these conditions is not guaranteed.
2
These signals are designed to withstand LVdd + 0.5 V DC when LVdd is con-
nected to a 3.3 V or 5.0V DC power supply.
3
LVdd input tolerant signals: PCI interface, EPIC control, and OSC_IN signals.
4
See Section 1.9, “Ordering Information,” for details on a modied voltage
(Vdd) version device.
Cautions:
5
Input voltage (VIN) must not be greater than the supply voltage
(Vdd/AVdd/AVdd2/LAVdd) by more than 2.5 V at all times, including during
power-on reset.
6
OVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8 V at any
time, including during power-on reset.
7
Vdd/AVdd/AVdd2/LAVdd must not exceed OVdd by more than 0.6 V at any
time, including during power-on reset.
8
GVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 1.8 V at any
time, including during power-on reset.
9
LVdd must not exceed Vdd/AVdd/AVdd2/LAVdd by more than 5.4 V at any
time, including during power-on reset.
10 LVdd must not exceed OVdd by more than 3.6 V at any time, including during
power-on reset.
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