參數(shù)資料
型號: MPC8240LZU200X
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁數(shù): 39/58頁
文件大小: 596K
代理商: MPC8240LZU200X
44
MPC8240 Integrated Processor Hardware Specications
Document Revision History
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common gure
of merit used for comparing the thermal performance of various microelectronic packaging technologies,
one should exercise caution when using only this metric in determining thermal management, because no
single parameter can adequately describe three-dimensional heat ow. The nal die-junction operating
temperature is not only a function of the component-level thermal resistance, but the system-level design
and its operating conditions. In addition to the component's power consumption, a number of factors affect
the nal operating die-junction temperature: airow, board population (local heat ux of adjacent
components), heat sink efciency, heat sink attach, heat sink placement, next-level interconnect
technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’s
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection,
and conduction) may vary widely. For these reasons, we recommend using conjugate heat-transfer models
for the board, as well as system-level designs.
1.8 Document Revision History
Table 19 provides a revision history for this hardware specication.
Table 19. Document Revision History
Document Revision
Substantive Change(s)
0
Preliminary release with some TBDs in the spec tables.
0.1
Updated notes for Table 2.
Replaced TBDs in Table 3 with values for Output High and Low Voltages.
Deleted 25/25/75 column from Table 5; inconsistent with PLL encoding 01000.
Updated minimum processor frequencies in Table 6 from 80 MHz to 100 MHz.
Updated values in Table 8. Spec 10b split for ow through and registered modes.
Updated PCI_HOLD_DEL value guidelines in Table 10 and Figure 10.
Relabeled DA[0:15] pins in opposite order and added Note 11 for TEST2 in Table 17.
Changed PLL congurations 01001 and 10001 in Table 18 to reserved congurations.
Updated PLL conguration 00010’s operation ranges in Table 18.
Revised TRST connection recommendations in Figure 22 for COP interface.
0.2
Added Note 4 to Table 2, updated Note and Caution numbers in Table 2 and Figure 2.
Modied Table 6.:
- Added 250 MHz column.
- Changed maximum PCI Input Frequency for 200 MHz part from 33 MHz to 66 MHz.
- Made one column common entries for Memory Bus and PCI Input Frequencies.
Revised Note 7 of Table 7. to indicate a feedback loop length of 6.25 inches (formerly
11.8 inches) corresponds to approximately 1 ns of delay.
Added 250 MHz column to Table 18..
Corrected Document Revision number for previous version of this document in
Table 19.. Document Revision was indicated as 1, should have been 0.1.
Removed P = Reduced Spec information from Figure 29; does not apply to MPC8240.
Added R = Modied Voltage Spec information to Figure 29.
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