參數(shù)資料
型號(hào)： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 31/58頁(yè)
文件大?。?/td> 596K
代理商： MPC8240LZU200X
MPC8240 Integrated Processor Hardware Specications
37
System Design Information
1.7.7 JTAG Conguration Signals
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the MPC8240
are available on the internet at www.mot.com/SPS/PowerPC/teksupport/tools/BSDL/) The TRST signal is
optional in the IEEE 1149.1 specication but is provided on all PowerPC implementations. While it is
possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable
power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since
the JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC
processors, simply tying TRST to HRST_CPU/HRST_CTRL is not practical. Note that the two hard reset
signals on the MPC8240 (HRST_CPU and HRST_CTRL) must be asserted and negated together to
guarantee normal operation.
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system
(typically a PC with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port of the processor,
with some additional status monitoring signals. The COP port requires the ability to independently assert
HRST_CPU/HRST_CTRL or TRST in order to fully control the processor. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, then the COP reset signals must be merged into these signals with logic.
The arrangement shown in Figure 24 allows the COP to independently assert HRST_CPU/HRST_CTRL
or TRST while insuring that the target can drive HRST_CPU/HRST_CTRL as well. The shown COP
header
adds
many
benets
including
breakpoints,
watchpoints,
register
and
memory
examination/modication, and other standard debugger features are possible through this interface.
Availability of these features can be as inexpensive as an unpopulated footprint for a header to be added
when needed. The CHKSTOP_IN signal access can be utilized by external test equipment/logic to signal a
check stop to the MPC8240.
The COP interface has a standard header for connection to the target system, based on the 0.025”
square-post 0.100” centered header assembly (often called a “Berg” header). The connector typically has
pin 14 removed as a connector key, as shown in Figure 24.
There is no standardized way to number the COP header shown in Figure 24; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin one (as with an IC). Regardless of the numbering, the signal placement recommended
in Figure 24 is common to all known emulators.
相關(guān)PDF資料
PDF描述
MPC8240LZU250X 32-BIT, 250 MHz, RISC PROCESSOR, PBGA352
MPC8240RZU266X 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
MPC8245LZU300X 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
MPC8245LZU350X 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
MPC8270CVVQLDA 32-BIT, 333 MHz, RISC PROCESSOR, PBGA480
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