參數(shù)資料
型號(hào)： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 40/58頁(yè)
文件大小： 596K
代理商： MPC8240LZU200X
MPC8240 Integrated Processor Hardware Specications
45
Document Revision History
0.3
Removed “PowerPC Platform compliant” from rst sentence on cover sheet.
Changed PCI 2.1 - “compatible” to “compliant” in Section 1.2, “Features.”
Updated Table 5 and its notes with preliminary power-consumption information.
Updated Table 6 removing 266 MHz frequency information.
Made corrections to Table 7.
Items 5a and 5b were changed to correct values for 66 MHz PCI_SYNC_IN.
OSC_IN Frequency Stability spec from 1000 ppm to 100 ppm.
Changed item 12b1 from 8.0 ns to 7.0 ns.
Added item 12b3, Output Valid for ROM accesses.
Table 11, item 2, “KAHLUA” terminology replaced with MPC8240.
Added EPIC Serial Interrupt Timing Section with two new gures causing
cross-references to subsequent gures to be updated.
Updated formatting of pin out Table 17.
Modied notes section of Table 17:
Split Note 3 into a new Notes 3 and 12. Notes 3, 5, and 7 cover internal pull-up
resistors active only during the reset state. Note 12 covers internal pull-up resistors
enabled at all times.
Note 11 has been revised.
Added Note 10 to SDA and SCL signals for consistency with MPC8240 User’s
Manual.
Added Note 10 to SMI and TBEN; inputs which should have pull-ups and for
consistency with reference designs.
Added Note 10 to SRESET and CHKSTOP_IN for consistency with Figure 24 (COP
Connector)
Added Notes 13 and 14 for output valid specications dependent upon memory
mode.
Added Note 15 for pins affected by programmable PCI output valid and hold time.
Added Notes 16 –18 relating to open drain pins.
Revised 200 MHz column to reect PCI_SYNC_IN 66 MHz upper limit.
Refs 1E and 1F not usable entries made to match others in the table.
Revised Notes 4 and 5 changing OSC_IN to PCI_SYNC_IN.
Removed 266 MHz column.
Removed Ref 0x06 for dual PLL bypass mode; added it to reserved list in Note 3.
Revised Note 4 describing PLL bypass mode.
Added missing cross-reference in Section 1.7.2, “Power Supply Voltage Sequencing,”
and corrected Schottky reference to the 1N5820 diodes.
Added Section 1.7.3, “Power Supply Sizing” on power supply sizing.
Modied internal pull-up resistor list in Section 1.7.6, “Pull-up/Pull-down Resistor
Requirements” to be consistent with Notes of Table 17; added reset conguration pin
pull-down resistor value recommendation.
Modied Figure 24, COP Connector Diagram:
Reversed direction of CKSTP_IN arrow to show it going in.
Added a pull-up resistor on TRST.
Changed R-spec device’s Vdd range from 2.5 - 2.625 V to 2.5 - 2.75 V.
Table 19. Document Revision History (Continued)
Document Revision
Substantive Change(s)
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