參數(shù)資料
型號(hào)： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 16/58頁(yè)
文件大?。?/td> 596K
代理商： MPC8240LZU200X
MPC8240 Integrated Processor Hardware Specications
23
Electrical and Thermal Characteristics
1.4.2.6 EPIC Serial Interrupt Mode AC Timing Specications
Table 14 provides the EPIC serial interrupt mode AC timing specications for the MPC8240.
Notes:
1
See the MPC8240 User’s Manual for a description of the EPIC Interrupt Control Register (EICR) describ-
ing S_CLK frequency programming.
2
S_RST, S_FRAME, and S_INT shown in Table 15 and Table 16 depict timing relationships to
sys_logic_clk and S_CLK and do not describe functional relationships between S_RST, S_FRAME, and
S_INT. See the MPC8240 User’s Manual for a complete description of the functional relationships
between these signals.
3
The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the
peripheral logic PLL; sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to
SDRAM_SYNC_IN feedback loop is implemented and the DLL is locked. See the MPC8240 User’s Man-
ual for a complete clocking description.
Figure 15. EPIC Serial Interrupt Mode Output Timing Diagram
Figure 16. EPIC Serial Interrupt Mode Input Timing Diagram
Table 14. EPIC Serial Interrupt Mode AC Timing Specifications
At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3 V
Num
Characteristic
Min
Max
Unit
Notes
1
S_CLK Frequency
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
1
2
S_CLK Duty Cycle
40
60
%
3
S_CLK Output Valid Time
–
6
ns
4
Output Hold Time
0
–
ns
5
S_FRAME, S_RST Output Valid
Time
–
1 sys_logic_clk period + 6
ns
2
6
S_INT Input Setup Time to S_CLK
1 sys_logic_clk period + 2
–
ns
2
7
S_INT Inputs Invalid (Hold Time)
to S_CLK
–
0
ns
2
S_CLK
S_RST
VM
S_FRAME
sys_logic_clk3
VM
4
3
5
4
6
S_CLK
S_INT
7
VM
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