參數(shù)資料
型號(hào)： MPC8240LZU200X
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 41/58頁(yè)
文件大?。?/td> 596K
代理商： MPC8240LZU200X
46
MPC8240 Integrated Processor Hardware Specications
Document Revision History
0.4
Modied DLL Lock Range with DLL_EXTEND = 1 equation in Table 7 from 0
≤ (NTclk/2
- tloop - tx0) ≤ 7 to 0 ≤(NTclk - Tclk/2 - tloop - tx0) ≤ 7.
Modied Figure 5 to only show Tloop up to 15 ns, not practical to implement Tloop
beyond 15 ns.
Modied DL[0:31] and DH[0:31] signal names to MDL[0:31] and MDH[0:31],
respectively, in Table 17 to be consistent with the MPC107 data bus naming
convention.
Several active low signal names in Table 17 inadvertently had the overline formatting
removed during the nal edit process of the previous revision. The signals are shown
correctly with overlines in this version. Signals affected were: DEVSEL, FRAME,
LOCK, PERR, SERR, STOP, TRDY, INTA, FOE, RCS0, RCS1, SDRAS, SDCAS, WE,
AS, HRST_CTRL, HRST_CPU, MCP, SMI, SRESET, CHKSTOP_IN, and MIV.
0.5
Removed references to GVdd = 2.5V until characterization of the memory interface at
this voltage has been completed.
Corrected Figure 2 power supply ramp-up time to be before the 100 microsecond PLL
relock time.
Deleted input leakage specication @ LVdd=5.5V.
Changed minimum “Input High Voltage for PCI only” from 0.5*OVdd to 0.65*OVdd
and added Note 6.
Changed condition on “Input Low Voltage,” VIL, from “All inputs except OSC_IN” to
“All inputs except PCI_SYNC_IN.”
Replaced minimum CVIH formula, 0.5*OVdd, with 2.4V value.
Replaced maximum CVIL formula, 0.3*OVdd, with 0.4V value.
Added Note 10 to Table 5.
Changed minimum memory bus frequency of operation from 25 MHz to 33 MHz in
Table 6 to coincide with information shown in PLL_CFG Table 18.
Updated clock specications in Table 7.
Updated input AC timing specications in Table 8.
Updated output AC timing specications in Table 9.
Replaced TBDs in Table 14 for specs 3, 5, & 6.
Table 17 renamed TEST3 (pin AF20) to TRIG_IN and renamed TEST4 (pin AC18) to
TRIG_OUT; moved both pins from Test/Conguration Signals group to Miscellaneous
Signals group.
Added external pull-up resistor to LVdd recommendation for INTA signal in Table 17
Added Note 19 to Table 17 about AVdd and LAVdd being internally connected; revised
Replaced HID1 column TBDs in Table 18 and deleted Note 1 resulting in renumbering
notes throughout Table 18.
Added Section 1.7.8, “PCI Reference Voltage - LVdd” about PCI reference voltage.
Added note in Section 1.9, indicating “L=Standard Spec.” part is only available in 200
MHz version of the device. Changed “XPC” to “MPC” for consistency with other
references in the document.
Table 19. Document Revision History (Continued)
Document Revision
Substantive Change(s)
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