參數(shù)資料
型號: MPC8240LZU200X
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352
文件頁數(shù): 23/58頁
文件大?。?/td> 596K
代理商: MPC8240LZU200X
MPC8240 Integrated Processor Hardware Specications
3
Features
The peripheral logic integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt
controller, I2O controller, and an I
2C controller. The 603e core is a full-featured, high-performance
processor with oating-point support, memory management, 16-Kbyte instruction cache, 16-Kbyte data
cache, and power management features. The integration reduces the overall packaging requirements and
the number of discrete devices required for an embedded system.
The MPC8240 contains an internal peripheral logic bus that interfaces the 603e core to the peripheral
logic. The core can operate at a variety of frequencies, allowing the designer to trade off performance for
power consumption. The 603e core is clocked from a separate PLL, which is referenced to the peripheral
logic PLL. This allows the microprocessor and the peripheral logic block to operate at different
frequencies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit data bus
(depending on memory data bus width) and a 32-bit address bus along with control signals that enable the
interface between the processor and peripheral logic to be optimized for performance. PCI accesses to the
MPC8240’s memory space are passed to the processor bus for snooping purposes when snoop mode is
enabled.
The MPC8240’s features serve a variety of embedded applications. In this way, the 603e core and
peripheral logic remain general-purpose. The MPC8240 can be used as either a PCI host or an agent
controller.
1.2 Features
Major features of the MPC8240 are as follows:
Peripheral logic
— Memory interface
– Programmable timing supporting either FPM DRAM, EDO DRAM, or SDRAM
– High-bandwidth bus (32/64-bit data bus) to DRAM
– Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices
– Supports 1-Mbyte to 1-Gbyte DRAM memory
– Contiguous memory mapping
– 16 Mbytes of ROM space
– 8-, 32-, or 64-bit ROM
– Supports bus-width writes to ash ROM or ash
– Write buffering for PCI and processor accesses
– Supports normal parity, read-modify-write (RMW), or ECC
– SDRAM data-path buffer
– Error injection/capture on data path
– Low voltage transistor-to-transistor logic (LVTTL)
– Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
address strobe
— 32-bit PCI interface operating at up to 66 MHz
– PCI 2.1-compliant
– PCI 5.0-V tolerance
– Support for PCI locked accesses to memory
– Support for accesses to all PCI address spaces
– Selectable big- or little-endian operation
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