參數(shù)資料
型號(hào)： MK50H27Q25
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 45/58頁(yè)
文件大小： 621K
代理商： MK50H27Q25
Table 1: PIN DESCRIPTION (continued)
SIGNAL NAME
PIN(S)
TYPE
DESCRIPTION
If CSR4<00> BCON = 1,
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO (O)
Byte selection is done using the BYTE line and DAL<00> latched during the
address portion of the bus transaction. MK50H27 drives BYTE only as a Bus
Master and ignores it when a Bus Slave. Byte selection is done as outlined
in the following table.
BYTE
DAL<00>
TYPE OF TRANSFER
LOW
ENTIRE WORD
LOW
HIGH
ILLEGAL CONDITION
HIGH
LOW
LOWER BYTE
HIGH
UPPER BYTE
BUSAKO is a bus request daisy chain output. If MK50H27 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK50H27 is
requesting the bus when it receives HLDA, BUSAKO will remain high
Note: All transfers are entire word unless the MK50H27 is configured for 8 bit
operation.
HOLD
BUSRQ
17
[19]
IO/OD
Pin 17 is configured through bit 0 of CSR4.
If CSR4<00> BCON = 0,
I/O PIN 17 = HOLD
HOLD request is asserted by MK50H27 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is
held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
I/O PIN 17 = BUSRQ
BUSRQ is asserted by MK50H27 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low
for the entire ensuing bus transaction.
ALE
AS
18
[20]
O/3S
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK50H27 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
I/O PIN 18 = ALE
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define
the address portion of the transfer. As ALE, the signal transitions from high
to low during the address portion of the transfer and remains low during the
data portion.
If CSR4<01> ACON = 1,
I/O PIN 18 = AS
As AS, the signal pulses low during the address portion of the bus transfer.
The low to high transition of AS can be used by a slave device to strobe the
address into a register.
AS is effectively the inversion of ALE.
HLDA
19
[21]
I
HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in
response to MK50H27’s assertion of HOLD, the MK50H27 is the Bus
Master. HLDA should be deasserted ONLY after HOLD has been released
by the MK50H27.
CS
20
[22]
I
CHIP SELECT indicates, when low, that the MK50H27 is the slave device
for the data transfer. CS must be valid throughout the entire transaction.
ADR
21
[23]
I
ADDRESS selects the Register Address Port or the Register Data Port. It
must be valid throughout the data portion of the transfer and is only used by
the chip when CS is low.
ADR
PORT
LOW
REGISTER DATA PORT
HIGH
REGISTER ADDRESS PORT
READY
22
[24]
IO/OD
When the MK50H27 is a Bus Master, READY is an asynchronous
acknowledgement from the bus memory that memory will accept data in a
WRITE cycle or that memory has put data on the DAL lines in a READ cycle.
MK50H27
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