參數(shù)資料
型號: MK50H27Q25
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 3/58頁
文件大小: 621K
代理商: MK50H27Q25
and receiver descriptor rings, etc.
The starting
address for the Initialization block, IADR, is de-
fined in the CSR2 and CSR3 registers inside the
MK50H27.
3.2.3 Signal Unit Repertoire
The frame format supported by the MK50H27 is
shown in Table A.
Each signal unit (SU) may
consist of a programmable number of leading flag
patterns (01111110), Backward Sequence Num-
ber, Backward Indicator Bit, Forward Sequence
Number, Forward Indicator Bit, Lenght Indicator
Field, followed by Signalling Information Octet,
Service Information Field, or Status Field, de-
pending on SU type, and then ended with a CK
(CRC) of either 16 or 32 bits, and a trailing flag
pattern. The number of leading flags transmitted
is programmable through the Mode Register in
the Initialization Block. Received signal units may
have as few as one flag between adjacent signal
units
The symbols and definitions for the signal unit
types handled by the MK50H27 are:
TABLE A - MK50H27 Signal Unit Repertoire
NAME
DEFINITION
MSU
Message Signal Unit
LSSU
Link Status Signal Unit
FISU
Fill In Signal Unit
F
Flag Sequence (01111110)
FSN
Forward Sequence Number
BSN
Backward Sequence Number
FIB
Forward Indicator Bit
BIB
Backward Indicator Bit
LI
Lenght Indicator
X
Reserved - programmed as zeroes
PRI
Priority Indication (JT-Q703 only)
SIO
Signalling Information Octe
SIF
Service Information Field
SF
Status Field
CK
Check bit Sequence (CRC)
MK50H27
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