參數(shù)資料
型號: MK50H27Q25
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 42/58頁
文件大?。?/td> 621K
代理商: MK50H27Q25
A 16-23
ALE
SYSCLK
BM0,1
READY
DAS
HLDA
HOLD
64
24
25
65
26
27
40
23
44
41
42
28
22
T 1
T 2
T 3
T 4
T 5
DAL0-15
READ
DALO
DALI
29
30
50
32
45
DATA IN
ADDR
31
49
48
47
46
48
ADDRESS
60
61
43
NOTES:
2. Output delay times are the maximum delay from the specifed edge to a valid output.
3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments
until the slave device returns READY.
1. This reduced DMA Cycle Time is selected by setting CSR2 bit 15, CYCLE =1.
Figure 7a: MK50H27 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>)
MK50H27
47/56
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