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參數(shù)資料
| 型號： | MK50H27Q25 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 30/58頁 |
| 文件大?。?/td> | 621K |
| 代理商： | MK50H27Q25 |
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4.3.2 Transmit Message Descriptor Entry
4.3.2.1 Transmit Message Descriptor 0 (TMD0)
BIT
NAME
DESCRIPTION
15
OWNA
When this bit is a zero either the HOST or the SLAVE PROCESSOR
owns this descriptor. When this bit is a one the MK50H27 owns this
descriptor.
The host sets the OWNA bit after filling the buffer pointed
to by the descriptor entry. The MK50H27 releases the descriptor after
transmitting
the buffer
and
receiving
the
proper acknow-
ledgement from the receiver. After the MK50H27, Host, or I/O ac-
celeration processor has relinquished ownership of a buffer, it may not
change any field in the four words that comprise the descriptor entry.
14
OWNB
This bit determines whether the Host or the Layer 3 I/O Processor owns
the buffer when OWNA is a zero.
The MK50H27 never uses this
bit. This bit is provided to facilitate use of a Layer 3 I/O processor.
13
SLF
Start of Long Signal Unit indicates that this is the first buffer used by the
MK50H27 for this signal unit. It is used for data chaining buffers. SLF
is set by the Host. When not chaining, SLF should be set to a one.
NOTE: A "Long Signal Unit" is any MSU which needs data chaining.
12
ELF
End of Long Signal Unit indicates that this is the last buffer used by the
MK50H27 for this signal unit. It is used for data chaining buffers. If
both SLF and ELF were set the signal unit would fit into one buffer
and no data chaining would be required.
ELF is set by the Host.
When not chaining, ELF should be set to a one.
11:08
0
Reserved, must be written as zeroes for CCITT/ITU operation.
11:10
PRIN
These bits determine the content of the Priority Indication bits of the
transmitted frame when JSS7E=1 (TTC JT-Q703 compliant mode).
07:00
TBADR
The High Order 8 address bits of the buffer pointed to by this descriptor.
This field is written by the Host and unchanged by MK50H27.
4.3.2.2 Transmit Message Descriptor 1 (TMD1)
BIT
NAME
DESCRIPTION
15:00
TBADR
The Low Order 16 address bits of the buffer pointed to by this descriptor
TBADR is written by the Host and unchanged by MK50H27.
The
least significant bit is zero since the descriptor must be word aligned.
1
5
1
4
1
3
0
7
0
8
1
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
TBADR<15:00>
0
1
5
1
0
1
4
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
00
TBADR<23:16>
O
W
N
A
O
W
N
B
S
L
F
E
L
F
PRIN
MK50H27
36/56
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MK50H27Q33B | 功能描述:射頻無線雜項(xiàng) SS7 Controller 33MHz RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
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| MK50H28 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER |
| MK50H28DIP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER |
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