參數(shù)資料
型號： MK50H27Q25
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 38/58頁
文件大?。?/td> 621K
代理商： MK50H27Q25
AC TIMING SPECIFICATIONS CONTINUED - MK50H27 -25
TA = 0
°C to 70 °C, VCC = +5 V ±5 percent, unless otherwise specified.
No
Signal
Symbol
Parameter
Notes
Min.
Typ.
Max.
Units
13
RCLK
TRCT
RCLK period
20
ns
14
RCLK
TRCH
RCLK high time
8
ns
15
RCLK
TRCL
RCLK low time
8
ns
16
RCLK
TRCR
Rise time of RCLK
0
8
ns
17
RCLK
TRCF
Fall time of RCLK
0
8
ns
18
RD
TRDR
RD data rise time
0
8
ns
19
RD
TRDF
RD data fall time
0
8
ns
20
RD
TRDH
RD hold time after rising edge of RCLK
2
ns
21
RD
TRDS
RD setup time prior to rising edge of
RCLK
8ns
22 ALE/DAS
TDOFF
Bus Master driver disable
Output Delay
0
20
ns
23 ALE/DAS
TDON
Bus Master driver enable after rising
edge T1 SYSCLK
Output Delay
0
20
ns
24
HLDA
THHA
Delay to falling edge of HLDA from
falling edge of HOLD (Bus Master)
0ns
25
HLDA
THLAH
HLDA input setup time
10
ns
26
HLDA
THLAS
Delay to rising edge HLDA from rising
edge HOLD
10
ns
27
A
TXAS
Address setup time
Output Delay
30
ns
28
A
TXAH
Address hold time
Output Delay
20
ns
29
DAL
TAS
Address setup time
Output Delay
35
ns
30
DAL
TAH
Address hold time
Output Delay
0
20
ns
31
DAL
TRDAS
Data setup time (Bus Master read)
15
ns
32
DAL
TRDAH
Data hold time (Bus Master read)
10
ns
33
DAL
TWAH
Address hold time (Bus Master write)
Output Delay
15
ns
34
DAL
TWDS
Data setup time (Bus Master write)
Output Delay
25
ns
35
DAL
TWDH
Data hold time (Bus Master write)
Output Delay
25
ns
36
DAL
TSRDS
Data setup time (Bus Slave read)
25
ns
37
DAL
TSRDH
Data hold time (Bus slave read)
25
ns
38
DAL
TSWDH
Data hold time (Bus slave write)
10
ns
39
DAL
TSWDS
Data setup time (Bus slave write)
10
ns
40
ALE
TALES
ALE setup time
Output Delay
30
ns
41
ALE
TALHB
ALE hold time (asserted to de-
asserted) (DMA Burst)
Output Delay
15
ns
42
ALE
TALHS
ALE hold time (asserted to 3-State)
(Single DMA cycle)
Output Delay
20
ns
43
DAS
TDASS
DAS setup time from falling edge of T2
SYSCLK (Bus Master)
Output Delay
25
ns
44
DAS
TDASH
DAS hold time from rising edge of
SYSCLK (Bus Master)
Output Delay
5
15
ns
45 DALI/DALO
BM)/BM1
TBMDE
Bus Master driver enable (from 3-
State to driven) (Bus Master)
Output Delay
25
ns
46
DALI
TRIS
DALI setup time (Bus Master read)
Output Delay
15
ns
47
DALI
TRIH
DALI hold time (Bus Master read)
Output Delay
25
ns
48
DALI
TBMDD
Bus Master driver disable (from driven
to 3-State) (Bus Master)
Output Delay
20
ns
MK50H27 -25
MK50H27
43/56
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