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參數(shù)資料
| 型號： | MK50H27Q25 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 13/58頁 |
| 文件大?。?/td> | 621K |
| 代理商： | MK50H27Q25 |
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the receipt of an MSU after having entered congestion. This primitive
indicates that the remote node congestion has abated.
4.1.2.3 Control and Status Register 2 (CSR2)
RAP<3:1> = 2
BIT
NAME
DESCRIPTION
15
CYCLE
Setting this bit selects a shorter DMA cycle (5 vs 6 SYSCLKs for bursting
or 5 vs 7 SYSCLKs for single DMA). See Figures 7a and 8a for details.
14
ESEN
Extended Scaler Enable. Setting this bit enables the use of the 16-bit
timer pre-scaler at IADR+24 rather than the 8-bit Scaler at IADR+02.
Using the 16-bit Scaler allows longer timer values at higher SYSCLK
rates. Set ESEN=0 for backward compatibility with the MK50H27.
13
0
Reserved, must be written as zeroes.
12
RSUTE
Received SU Timer Enable. Setting this bit enables a timer for detecting
more than 32xTP time between received Signal Units. If RSUTE=1,
PPRIM=5 will be issued upon expiry of the Received SU Timer. A typi-
cal use for RSUT is to detect breaking of the serial data connection.
11:09
0
Reserved, must be written as zeroes.
08
JSS7E
Japanese SS7 Enable. Setting this bit enables TTC JT-Q703 compliance.
When JSS7E=1 the MK50H27 will align using only SIEs, timers Tf, Ts,
To, Ta, and Te will be activated appropriately, and the SUERM will act
in accordance with JT-Q703 requiring interchanging the location of the
T and D fields in the Initialization Block. If JSS7E=1 the MK50H27 will
NOT comply with all CCITT/ITU, ANSI, or AT&T specifications.
07:00
IADR
The high order 8 bits of the address of the first word (lowest address)
in the Initialization Block.
IADR
must
be written by the Host
prior to issuing an INIT primitive.
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1> = 3
BIT
NAME
DESCRIPTION
15:00
IADR
The low order 16 bits of the address of the first word (lowest address)
in the Initialization Block. Must be written by the Host prior to issu-
ing an INIT primitive. The Initialization block must begin on a word
boundary.
1
5
1
0
1
4
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
IADR<23:16>
0
000
C
Y
C
L
E
S
E
N
R
S
U
T
E
J
S
7
E
1
5
1
0
1
0
9
1
2
1
0
8
0
3
0
7
0
2
0
6
0
5
0
4
0
1
0
1
3
0
IADR <15:00>
MK50H27
20/56
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK50H27Q33B | 功能描述:射頻無線雜項 SS7 Controller 33MHz RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
| MK50H27TQ25B | 制造商:STMicroelectronics 功能描述:SS7 HDLC CONTROL - Tape and Reel |
| MK50H27TQ33B | 功能描述:電信集成電路 SS7 Controller 33MHz RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| MK50H28 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER |
| MK50H28DIP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER |
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