參數(shù)資料
型號(hào)： MK50H27Q25
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 51M bps, SERIAL COMM CONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 28/58頁(yè)
文件大?。?/td> 621K
代理商： MK50H27Q25
4.3 Receive and Transmit Descriptor Rings
Each descriptor ring in memory is a 4 word entry. The following is the format of the receive and transmit
descriptors.
4.3.1 Receive Message Descriptor Entry
4.3.1.1 Receive Message Descriptor 0 (RMD0)
BIT
NAME
DESCRIPTION
15
OWNA
When this bit is a zero either the HOST or the I/O ACCELERATION
PROCESSOR owns this descriptor.
When this bit is
a
one
the
MK50H27 owns this descriptor. The chip clears the OWNA bit af-
ter filling the buffer pointed to by the descriptor entry provided a valid
signal unit has been received.
The Host sets the OWNA bit after
emptying the buffer.
Once the MK50H27,
Host, or I/O accelera-
tion processor has relinquished ownership of
a buffer, it may not
change any field in the four words that comprise the descriptor entry.
14
OWNB
This bit determines whether the Host or the Layer 3 I/O Processor owns
the buffer when OWNA is a zero.
The MK50H27 never uses this
bit. This bit is provided to facilitate use of a Layer 3 I/O processor.
13
SLF
Start of Long Signal Unit indicates that this is the first buffer used
by MK50H27 for this signal unit. It is used for data chaining buffers.
SLF is set by the MK50H27.
NOTE: A "Long Signal Unit" is any
MSU which needs data chaining.
12
ELF
End of Long Signal Unit indicates that this the last buffer used by
MK50H27 for this signal unit. It is used for data chaining buffers. If
both SLF and ELF were set, the signal unit would fit into one buffer
and no data chaining would be required. ELF is set by the MK50H27.
11:08
0
Reserved, must be written as zeroes for CCITT/ITU compliant operation.
11:10
PRIN
These bits indicate the content of the Priority Indication bits of the
received frame when JSS7E=1 (TTC JT-Q703 compliant mode).
07:00
RBADR
The High Order 8 address bits of the buffer pointed to by this descriptor.
This field is written by the Host and unchanged by MK50H27.
1
5
1
4
1
3
0
7
0
8
1
0
1
2
0
1
0
2
0
3
0
4
0
5
0
9
0
6
RBADR<23:16>
O
W
N
A
O
W
N
B
S
L
F
E
L
F
00
PRIN
MK50H27
34/56
相關(guān)PDF資料
PDF描述
MK50N512CLQ100 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
MK50X256CMC100 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
MK50N512CMC100 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA121
MK51DN512ZCLQ10 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
MK51DN256ZCMD10 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MK50H27Q33B 功能描述:射頻無(wú)線雜項(xiàng) SS7 Controller 33MHz RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel
MK50H27TQ25B 制造商:STMicroelectronics 功能描述:SS7 HDLC CONTROL - Tape and Reel
MK50H27TQ33B 功能描述:電信集成電路 SS7 Controller 33MHz RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
MK50H28 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER
MK50H28DIP 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MULTI LOGICAL LINK FRAME RELAY CONTROLLER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*