參數(shù)資料
型號(hào): MD2534-D2G-X-P
廠商: SANDISK CORP
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝: 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁數(shù): 8/87頁
文件大小: 1675K
代理商: MD2534-D2G-X-P
Rev. 1.2
Product Overview
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
16
92-DS-1205-10
2.2.2
9x12/10x14/12x18 FBGA Signal Description
mDOC H3 (115 ball) package ball designations are listed in the signal descriptions, presented in
logic groups, in Table 1.
Table 1: Demux Interface Signal Description
Signal
Ball No.
Signal Type
1
Description
Signal
Direction
System Interface
A[16:15]
A[14:13]
A[12:11]
A[10:8]
A[7:4]
A[3:0]
F10, E10
E4, F4
E8, D8
G7, F7, D7
D3, E3,
F3, G3
E2, F2,
G2, H2
A[12:0] ST
A[16:13]IN/PD
Address bus.
Input
D[7:6]
D[5:3]
D[2:0]
K8, H7
L7, J6, J5
L4, H4, K3
ST
Data bus, low byte.
Input/output
D[15:14]
D[13:12]
D[11:8]
J8, L8
J7, K7
L5, K4, J4,
L3
ST
Data bus, high byte.
Input/output
CE#
J2
ST
Chip Enable, active low.
Input
OE#
J3
ST
Output Enable, active low.
Input
WE#
D6
ST
Write Enable, active low
Input
Configuration
GPIO_TIMER
E1
ST/PU
RSRVD. This signal may be left floating or
pulled up.
Input/output
ID0
G8
PD
Identification. Configuration control to
support up to two chips cascaded in the
same memory window.
Chip 1: ID0 = VSS
Chip 2: ID0 = VCCQ
Input
LOCK#
F8
ST
Lock, active low. When active, provides full
hardware data protection of selected
partitions.
Input
Control
WARM_RST#
J9
ST/PU
RSRVD. This signal may be left floating or
pulled up.
Input
BUSY#
F5
CMOS output
Busy. Active low. Indicates that mDOC is
initializing and should not be accessed5
Output
RSTIN#
E5
ST/PU
Reset, active low.
input
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