參數(shù)資料
型號： MD2534-D2G-X-P
廠商： SANDISK CORP
元件分類： 存儲控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝： 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁數(shù)： 45/87頁
文件大?。?/td> 1675K
代理商： MD2534-D2G-X-P
Rev. 1.2
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
5
92-DS-1205-10
REVISION HISTORY
Doc. No
Revision
Date
Description
Reference
0.1
January 2006
Preliminary version
RSRVD balls left floating changed
from a recommendation to a
requirement
Section 2
Demux (Standard) I/F Ball H9
changed from RSRVD to VSS
Section 2.2
Ballout change – Some NC balls
removed, resulting in 115 balls for
all products
Section 2.2
Ball H2 changed from DPD to A0
Sections 2.2 and 2.3
Details on internal pull up and pull
down resistors added
Sections 2.2.2 and 2.3.2
DPD signal removed (replaced with
A0, which should be connected to
CPU A0 or to VSS)
Sections 2, 2.2.2 and
Balls G1,H1,J1,K1 marked as
reserved
Ball G4 changed from RSRVD to
VCCQ
Sections 2.2.2 and 2.3.2
Ball D9 changed from NC to
RSRVD
Section 2.3.2
Modes of operation diagram
updated
Section 5
“Normal mode” name changed to
“Turbo mode”
Section 5
8KB address space settings added
Section 6.5
Added register addresses for 8KB
address space
Section 7
Burst mode can only be used in
conjunction with mDOC H3 DMA
functionality
Section 9.8.2
Operating Conditions updated
Section 10.3
Asynchronous boot mode timing
diagram added
Section 10.3.1
Multiplexed timing updated
Section 10.3.4
Section 10.3.5
Power up timing updated
Section 10.3.11
92-DS-1205-10
0.2
June 2006
Mechanical drawing updated
(removed balls from 12x18mm
drawing)
Section 10.4.3
相關(guān)PDF資料
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MD2533-D16G-X-P/Y FLASH MEMORY DRIVE CONTROLLER, PBGA115
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