參數(shù)資料
型號： MD2534-D2G-X-P
廠商： SANDISK CORP
元件分類： 存儲控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝： 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁數(shù)： 19/87頁
文件大?。?/td> 1675K
代理商： MD2534-D2G-X-P
Rev. 1.2
Theory of Operation
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
26
92-DS-1205-10
Flash IF – Physical interface to the Flash Media.
Power and Timing – Analog and clock circuits to provide power and timing for the
H3 controller and flash.
Embedded CPU – Runs Embedded TrueFFS SW and mDOC H3 controller
firmware.
3.2
Host Interface
3.2.1
Demux (NOR-Like) Interface
The host interface block provides an easy-to-integrate NOR-like (also SRAM and EEPROM-
like) interface to mDOC H3, enabling various CPU interfaces, such as a local bus, ISA bus, NOR
interface, SRAM interface, EEPROM interface or any other compatible interface. In addition, the
NOR-like interface enables direct access to the Programmable Boot Block to permit XIP
(Execute-In-Place) functionality during system initialization.
A1-A16 address lines enable access to the mDOC H3 128KB memory window. When migrating
from mDOC G3/G4/H1 without changing the PCB, thus using only A1-A12 address lines,
mDOC H3 exports 8KB memory window, like in mDOC G3/G4 and H1.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and
write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted.
Similarly, a read cycle occurs while both the CE# and OE# inputs are asserted. Note that mDOC
H3 does not require a clock signal. The CE#, WE# and OE# signals trigger the controller (e.g.,
system interface block, bus control and data pipeline) and flash access.
The Reset-In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase.
The Interrupt Request (IRQ#) signal is used to indicate completion of assorted operations. Using
this signal frees the CPU to run other tasks, continuing read/write operations with mDOC H3
only after the IRQ# signal has been asserted and an interrupt handling routine (implemented in
the OS) has been called to return control to the DOC Driver.
The DMARQ# output is used to control DMA operations, and the CLK input is used to support
Burst operation when reading flash data. See Section 10.3 for further information.
3.2.2
Multiplexed Interface
In this configuration, the address and data signals are multiplexed. The AVD# input is driven by
the host AVD# signal, and the D[15:0] signals, used for both address inputs and data, are
connected to the host AD[15:0] bus. While AVD# is asserted, the host drives AD[15:0] with bits
[16:1] of the address.
This interface is automatically used when a falling edge is detected on AVD#. This edge must
occur after RSTIN# is de-asserted and before the first read or write cycle to the controller.
相關(guān)PDF資料
PDF描述
MD2533-D16G-X-P/Y FLASH MEMORY DRIVE CONTROLLER, PBGA115
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