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參數(shù)資料
| 型號(hào)： | MD2534-D2G-X-P |
| 廠商： | SANDISK CORP |
| 元件分類： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA115 |
| 封裝： | 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115 |
| 文件頁(yè)數(shù)： | 26/87頁(yè) |
| 文件大?。?/td> | 1675K |
| 代理商： | MD2534-D2G-X-P |
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Rev. 1.2
mDOC H3 Modes of Operation
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
32
92-DS-1205-10
The above power modes are separated into two main groups:
Work mode group – in which the device is active and performs various transactions.
Idle mode group – in which the device is not active.
The power mode is determined as follows:
Assertion of the RSTIN# signal sets the device in Reset state.
Upon power up the device enters its pre-configured work mode.
Default work mode is Turbo mode. The default can be changed to PowerSave mode
and vice-versa using S/W API.
Once in any idle mode the device will move to work mode upon any transaction. It
may return to idle mode upon inactivity, if so configured.
Entry and exit to/from Deep Power-Down mode is described below.
5.1
Reset State
While in Reset State, mDOC H3 ignores all write transactions and returns undefined values in
response to any read access.
5.2
Turbo Mode
This mode is defined as a "work mode" and is optimized for performance. All internal clocks are
set to maximal work frequency.
In this mode all standard operations involving the flash memory can be performed.
5.3
Power Save Mode
This mode is defined as a "work mode" and is optimized for balance between power
consumption and performance. Balance is achieved by setting internal clocks to predefined
optimal settings.
In this mode all standard operations involving the flash memory can be performed.
5.4
Standby Mode
mDOC H3 enters standby mode upon device inactivity. In Standby mode the clock of most
internal cores is either disconnected or reduced to a minimum. There is no wake-up time penalty
when switching back to working mode.
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