參數(shù)資料
型號(hào)： MD2534-D2G-X-P
廠商： SANDISK CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PBGA115
封裝： 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件頁數(shù)： 57/87頁
文件大小： 1675K
代理商： MD2534-D2G-X-P
Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
60
92-DS-1205-10
Figure 19: Multiplexed Write Burst Mode
9.9
Device Cascading
Up to two devices can be cascaded with no external decoding circuitry. Figure 19 illustrates the
configuration required to cascade two devices on the host bus (only the relevant cascading
signals are included in this figure, although all other signals must also be connected). All balls of
the cascaded devices must be wired in common, except for ID0. The ID ball values determine the
identity of each device – the first device is identified by connecting the ID ball as 0, and the
second device by connecting the ID ball as 1. Systems that use only one mDOC H3 should
connect ID0 to GND.
Figure 19: mDOC H3 Cascaded Configuration
ID0
CE#
OE#
WE#
CE#
WE#
OE#
VSS
ID0
CE#
OE#
WE#
VCCQ
2nd
1st
相關(guān)PDF資料
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