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參數(shù)資料
| 型號： | MC68HC705CL48 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | TQFP-112 |
| 文件頁數(shù)： | 92/145頁 |
| 文件大?。?/td> | 673K |
| 代理商： | MC68HC705CL48 |
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GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05CL48
7-2
REV 2.0
7.2
PORT A
Port A is an 8-bit bidirectional port. The port A data register is at $0000 and the
data direction register (DDRA) is at $0003. Reset does not affect the data register,
but clears the data direction register, thereby returning the ports to inputs. Writing
a one to a DDR bit sets the corresponding port bit to output mode. In addition to
normal I/O port function, PTA0-PTA2 are also used as additional external interrupt
inputs and PTA3-PTA7 are also associated with the KEYBOARD interrupt
function. See Section 4.3.2 for detail description on External and Keyboard
interrupts.
7.3
PORT B
Port B is an 8-bit bidirectional port. The port B data register is at $0001 and the
data direction register (DDRB) is at $0004. Reset does not affect the data register,
but clears the data direction register, thereby returning the ports to inputs. Writing
a one to a DDR bit sets the corresponding port bit to output mode.
7.4
PORT C
Port C is an 8-bit bidirectional port which shares its pins with subsystems A-2-D,
SPI and Timer under the control of the A-2-D status and control register ADCSR,
the SPI control register SPCR and the Timer pin conguration register TIMCONF.
The port C data register is at $0002, the data direction register (DDRC) is at
$0005. Reset does not affect the data register, but clears the data direction,
thereby returning the ports to inputs. Writing a one to a DDR bit sets the
corresponding port bit to output mode. Writing a ‘1’ to the SPE-bit of the SPI
control register SPCR congures PTC[0:3] as dedicated SPI pins. Setting
CONF6-bit and CONF7-bit of the Timer pin conguration register TIMCONF to ‘1’
congures PTC6 and PTC7 as Timer input capture pins respectively.
PTC[4:5] will always be available as IO port pins even after the ADON-bit is set.
When ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control
register is set to select channel-2, PTC[4] becomes an A-2-D input pin. When
ADON-bit is set to ‘1’ and the CH[2:0] bits of the A-2-D status and control register
is set to select channel-3, PTC[5] becomes an A-2-D input pin.
Table 7-1. summarizes the PORT C function when used as sub-system pins.
Table 7-2. PORT C I/O Conguration
PORT C
I/O Mode
Sub-System Function
PTC0
Input
Output
SCK: SPI slave clock-in (MSTR = ‘0’, SPE=1).
SCK: SPI master clock-out (MSTR = ‘1’, SPE=1).
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