參數(shù)資料
型號(hào)： MC68HC705CL48
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 1.802 MHz, MICROCONTROLLER, PQFP112
封裝： TQFP-112
文件頁數(shù)： 106/145頁
文件大小： 673K
代理商： MC68HC705CL48
June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
TIMER
MOTOROLA
REV 2.0
8-11
Figure 8-5. Timer State Timing Diagram For Input Capture
8.1.4 Timer Control Register (TCR)
The timer control registers TCR is a read/write register. Five bits control interrupts
associated with the timer status register ags IC1F, IC2F, OC1F, OC2F and TOF.
The other two bits control which edge is signicant to the input capture edge
detector (i.e., negative or positive). The timer control register and the free running
counter are the only sections of the timer affected by reset. The timer control
registers are illustrated below by a denition of each bit.
76543210
TCR
$0011
READ
IC1IE
IC2IE
OC1IE
OC2IE
TOIE
IEDG2
IEDG1
WRITE
RESET
00000
X
U
U = UNAFFECTED
Internal Processor Clock
Internal
Timer
Clocks
T00
T01
T10
T11
Counter (16 bit) $FFEB
$FFEC
$FFED
$FFEE
$FFEF
Input Edge
note
Input Capture Latch
Capture Register
$????
$FFED
Input Capture Flag (ICF)
NOTE: If the input edge occurs in the shaded area from one timer state T10 to the other
timer state T10 the Input Capture Flag is set during the next state T11.
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