參數(shù)資料
型號(hào): MC68HC705CL48
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1.802 MHz, MICROCONTROLLER, PQFP112
封裝: TQFP-112
文件頁數(shù): 134/145頁
文件大?。?/td> 673K
代理商: MC68HC705CL48
June 11, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL48
CALLER-ID
MOTOROLA
REV 2.0
11-5
Figure 11-6. Power Up Sequence from WAIT Mode
11.6
DATA INTERFACE
The demodulated data from this module is available in bit-serial and 8-bit format.
The serial data can be read from CIDSD (bit 2) of the CLCSR2 register and the 8-
bit data is available from the Caller_ID data register CDDR. This data includes the
alternate 0 and 1 pattern, 150 ms marking which precedes data. At all other times
the demodulator output bit is high.
The Caller_ID data ready ag CDRF bit-2 of CLCSR3 will be set to indicate that
the 8-bit data is ready to be read. The data ready ag will generate an CPU
interrupt if the data ready interrupt enable DRIE bit-3 of CLCSR3 is set and the I-
bit of the CCR is cleared. The Caller_ID data register CDDR acts as data buffer for
the serial to parallel data conversion register and should be read by the CPU
within 8.3msec after receiving the interrupt. Failure to do so will result data lost.
Reading the Caller_ID data register CDDR clears the Caller_ID data ready ag.
Figure 11-9 shows the timing diagram for the serial to parallel data conversion.
CPU WAIT MODE
CDPW?
POWER ON
CDIE?
CD INTERRUPT
YES
WAKE UP CPU
NO
CARRIER DETECT
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