參數(shù)資料
型號(hào)： MC68HC705CL48
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 1.802 MHz, MICROCONTROLLER, PQFP112
封裝： TQFP-112
文件頁數(shù)： 114/145頁
文件大小： 673K
代理商： MC68HC705CL48
GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
TIMER
MC68HC05CL48
8-18
REV 2.0
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 2016 cycles, the power-on reset circuit is released which again
clears the counter chain and allows the device to come out of reset. At this point, if
RESET is not asserted, the timer will start counting up from zero and normal
device operation will begin. When RESET is asserted any time during operation
(other than POR), the counter chain will be cleared.
8.2.4 Operation During Low Power Mode
The timer is cleared when going into STOP mode. When STOP is exited by an
external interrupt or an external RESET, the internal oscillator will resume,
followed by 2016 cycles internal processor stabilization delay. The timer is then
cleared and operation resumes.
The CPU clock halts during the WAIT mode, but the timer remains active. If the
interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT
mode.
76543210
CTCR
$0009
READ
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
WRITE
RESET
00000000
Table 8-1. RTI and COP Rates at 1.8MHz Bus Frequency
BUS FREQUENCY = 1.8 MHz
RT1:RT0
Div. Ratio
RTI Rate
COP Rate (RTIx7)
00
214
9.1 ms
63.7 ms
01
215
18.2ms
127.4 ms
10
216
36.4 ms
254.8 ms
11
217
72.8 ms
509.6 ms
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