參數(shù)資料
型號: MC68HC705CL48
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 1.802 MHz, MICROCONTROLLER, PQFP112
封裝: TQFP-112
文件頁數(shù): 11/145頁
文件大小: 673K
代理商: MC68HC705CL48
GENERAL RELEASE SPECIFICATION
June 11, 1997
MOTOROLA
PHASE-LOCKED LOOP
MC68HC05CL48
13-2
REV 2.0
13.1
PLL CONTROL AND STATUS REGISTER (PCSR $000D)
PON - PLL power on/off bit.
1 =
PLL is switched on.
0 =
PLL is switched off.
PCLK - PLL Clock select bit.
1 =
Use PLL clock.
0 =
Use external clock.
FREQ1 - Frequency select bit 1.
FREQ0 - Frequency select bit 0.
13.2
PLL OPERATIONS
The PLL consists of an on chip VCO, a phase comparator and a divider. A lter is
required to lter the phase comparator output to provide a DC signal to control the
VCO frequency Figure 13-1.
13.3
PLL LOCK TIME
The PLL will lock in less than 10msec after the PON-bit is set. The PCLK should
not be set before the PLL is locked.
13.4
PLL CLOCK FREQUENCY
When the PLL is in lock, the VCO output frequency is given by:
The VCO output frequency is further divided by a frequency divider circuit to give
three other frequencies as shown in Figure 13-1.
7
6
5
4
3
2
1
0
PCSR
$000D
READ
PON
PCLK
FREQ1
FREQ0
WRITE
RESET
0
X
0
X
Fvco = 114 * Fosc
where Fosc = oscillator frequency
Example: Fosc = 32.768kHz, Fvco = 3.604MHz.
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