- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98011 > MC68HC05CT4FN (MOTOROLA INC) 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC05CT4FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 84/142頁 |
| 文件大?。?/td> | 624K |
| 代理商： | MC68HC05CT4FN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁當(dāng)前第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets
General Release Specification
MC68HC05CT4 — Rev. 2.0
46
Resets
MOTOROLA
5.4 Internal Resets
The three internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, and the illegal address detector.
Termination of the external RESET input or the internal COP watchdog
timer are the only reset sources that can alter the operating mode of the
MCU. The other internal resets do not have any effect on the mode of
operation when their reset state ends.
5.4.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor bus clock
cycles (PH2) after the oscillator becomes active.
The POR generates the RST signal that resets the CPU. If any other
reset function is active at the end of this 4064-cycle delay, the RST
signal remains in the reset condition until the other reset condition(s)
end. During the POR, the RESET pin is forced low.
5.4.2 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. Regardless of an internal or external
RESET, the MCU comes out of a COP reset according to the standard
rules of mode selection.
The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
5.4.2.1 Resetting the COP
Writing a zero to the COPF bit prevents a COP reset. This action resets
the counter and begins the timeout period again. The COPF bit is bit 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05J1P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| MC68HC05J1CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HC05J1DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HC05J1CP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| MC68HC05JB4DWR2 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05D9 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-bit microcomputer with PWM outputs and LED drive |
| MC68HC05E0 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05E0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC05E16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16256 bytes of user ROM, 320bytes of EPROM and 352 bytes of RAM |
| MC68HC05E16/D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16256 bytes of user ROM, 320bytes of EPROM and 352 bytes of RAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。