參數(shù)資料
型號(hào): MC68HC05CT4FN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 76/142頁
文件大?。?/td> 624K
代理商: MC68HC05CT4FN
Interrupts
Hardware Interrupts
MC68HC05CT4 Rev. 2.0
General Release Specification
MOTOROLA
Interrupts
39
NON-DISCLOSURE
AGREEMENT
REQUIRED
4.6 Hardware Interrupts
All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The two
types of hardware interrupts are explained in the following sections.
4.7 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in Figure 4-2.
NOTE:
The BIH and BIL instructions will apply only to the level on the IRQ pin
itself, and not to the output of the logic OR function with the port C IRQ
interrupts. The state of the individual port C pins can be checked by
reading the appropriate port C pins as inputs.
Figure 4-2. IRQ Function Block Diagram
The IRQ pin is one source of an external interrupt. All port C pins
(PC0–PC7) act as other external interrupt sources if the keyscan feature
is enabled as specified by the user.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to:
Falling edge on the IRQ pin
Falling edge on any port C pin with keyscan enabled
IRQ
LATCH
R
IRQ PIN
LEVEL
(MASK OPTION)
TO IRQ
PROCESSING
IN CPU
PORT C
TO BIH & BIL
INSTRUCTION
SENSING
RST
IRQ VECTOR FETCH
VDD
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