參數(shù)資料
型號(hào)： MC68HC05CT4FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 124/142頁
文件大?。?/td> 624K
代理商： MC68HC05CT4FN
NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer
General Release Specification
MC68HC05CT4 — Rev. 2.0
82
Core Timer
MOTOROLA
TOFC — Timer Overflow Flag Clear
When a logic 1 is written to this bit, CTOF is cleared. Writing a logic 0
has no effect on the CTOF bit. This bit always reads as zero.
RTFC — Real-Time Interrupt Flag Clear
When a logic 1 is written to this bit, RTIF is cleared. Writing a logic 0
has no effect on the RTIF bit. This bit always reads as zero.
RT1 and RT0 — Real-Time Interrupt Rate Select
These two bits select one of four taps from the real-time interrupt
circuit. See Table 10-1. Reset sets these two bits, which selects the
slowest periodic rate and gives the maximum time in which to alter
these bits if necessary. Care should be taken when altering RT0 and
RT1 if the timeout period is imminent or uncertain. If the selected tap
is modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing RTI taps.
Table 10-1. RTI and COP Rates at 2.048 MHz
RTI Rate
2.048 MHz
RT1
and RT0
Minimum COP Rates
2.048 MHz
8 ms
214/E
00
(217–214)/E
56 ms
16 ms
215/E
01
(218–215)/E
112 ms
32 ms
216/E
10
(219–216)/E
224 ms
64 ms
217/E
11
(220–217)/E
448 ms
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