參數(shù)資料
型號: MC68HC05CT4FN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 106/142頁
文件大?。?/td> 624K
代理商: MC68HC05CT4FN
NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timer
General Release Specification
MC68HC05CT4 Rev. 2.0
66
16-Bit Timer
MOTOROLA
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transitions from $FFFF to
$0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are
accessed
Reset clears this bit.
Bits 0–4 — Not Used
Always read zero.
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
The timer status register is read or written when TOF is set.
The MSB of the free-running counter is read but not for the
purpose of servicing the flag.
The counter alternate register at address $1A and $1B contains the
same value as the free-running counter at address $18 and $19; this
alternate register can be read at any time without affecting the timer
overflow flag in the timer status register.
8.8 Timer During Wait Mode
The CPU clock halts during wait mode, but the timer remains active if
turned on prior to entering wait mode. If interrupts are enabled, a timer
interrupt will cause the processor to exit wait mode.
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