參數(shù)資料
型號: MC68HC05CT4FN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 129/142頁
文件大?。?/td> 624K
代理商: MC68HC05CT4FN
Dual Phase-Locked Loop (PLL)
Registers
MC68HC05CT4 Rev. 2.0
General Release Specification
MOTOROLA
Dual Phase-Locked Loop (PLL)
87
NON-DISCLOSURE
AGREEMENT
REQUIRED
11.3 Registers
The PLL has one 12-bit programmable counter, two 16-bit
programmable counters, and one control register.
11.3.1 Dual Control Register
The PLLCR contains bits that affect the operation of the PLL.
PLS1 and PLS0 — PLL Reference Counter Select
These bits select between the PLL reference counter MUX outputs.
This output signal then drives the phase detectors.
RXON — RX Counter Enable
When set, this bit enables the PLL receive counter.
When clear, it stops the receive counter in a reset state to save power.
RXON also shuts off the associated phase detector and holds it in
three-state. Initializing the receive counter before it is enabled is
recommended.
Address:
$000A
Bit 7
654321
Bit 0
Read:
TLOCK
RLOCK
REFON
TXON
RXON
PLS1
PLS0
Write:
Reset:
00000000
= Unimplemented
Figure 11-2. Dual PLL Control Register
Table 11-1. PLL Reference Counter Select
PLS1 and PLS0
PLL Reference Counter Output
00
÷12-Bit Counter
01
÷4 After 12-Bit Counter
10
÷5 After 12-Bit Counter
11
÷25 After 12-Bit Counter
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