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參數(shù)資料
| 型號(hào)： | MC68HC05CT4FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 4/142頁(yè) |
| 文件大?。?/td> | 624K |
| 代理商： | MC68HC05CT4FN |
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Comparators
Comparator Control/Status Register
MC68HC05CT4 — Rev. 2.0
General Release Specification
MOTOROLA
Comparators
101
NON-DISCLOSURE
AGREEMENT
REQUIRED
13.3 Comparator Control/Status Register
CMP3 — Comparator 3 Output
This bit is implemented in two ways: as a real-time comparator output
or as a latched interrupt source. The state of CM3IE determines which
implementation is selected.
CM3IE = 0 (nonlatched mode) — This status bit is cleared only by two
means:
1. Clearing CM3IE while the voltage at CMP3+ is less than CMP3–
2. By an external reset
CM3IE = 1 (latched mode) — This latched status bit is set when the
voltage at CMP3+ (PD0) is larger than that of CMP3– (internal voltage
reference ~ 2 VDD/3). An interrupt is then initiated ($1FFA–$1FFB).
CMP2 — Comparator 2 Output
This status bit is set when the voltage at CMP12+ is larger than that
of CMP2–, otherwise, it is cleared. Reset clears this bit because the
comparator is disabled.
CMP1 — Comparator 1 Output
This status bit is set when the voltage at CMP12+ is larger than that
of CMP1–, otherwise, it is cleared. Reset clears this bit because the
comparator is disabled.
Address:
$0022
Bit 7
654321
Bit 0
Read:
CMP3
CMP2
CMP1
CM3IE
0
CEN3
CEN2
CEN1
Write:
Reset:
00000000
= Unimplemented
Figure 13-2. Comparator Control/Status Register (CMPCSR)
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