參數(shù)資料
型號: MC56F8000RM
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 9/124頁
文件大?。?/td> 1880K
代理商: MC56F8000RM
Architecture Block Diagram
56F8013 Technical Data, Rev. 2
Freescale Semiconductor
Preliminary
9
Figure 1-2 Peripheral Subsystem
Table 1-1 Bus Signal Names
Name
Function
Program Memory Interface
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
pdb_m[15:0]
Program data bus for instruction word fetches or read operations.
cdbw[15:0]
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
Primary Data Memory Interface Bus
xab1[23:0]
Primary data address bus. Capable of addressing bytes
1
, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
1. Byte accesses can only occur in the bottom half of the memory address space. The Most Significant Bit (MSB)
of the
address will be forced to 0.
cdbr_m[31:0]
Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0]
Primary core data bus for memory writes. Addressed via xab1 bus.
Secondary Data Memory Interface
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
xdb2_m[15:0]
Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
IPBus
GPIO A
Interrupt
Controller
To/From IPBus Bridge
GPIO B
GPIO C
CLKGEN
(ROSC / PLL /
CLKIN)
POR & LVI
SIM
GPIO D
Low-Voltage Interrupt
System POR
COP Reset
RESET / GPIOA7
COP
GPIOA
n
GPIOB
n
GPIOC
n
GPIOD
n
(Continues on
Figure 1-3
)
8
8
6
4
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